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<hr><h1>DACU<br>
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[<a class="el" href="group__pavr__hwres.html">Hardware resources</a>]</small>
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<dl compact><dt><b>
Overview</b><dd>
The Data Address Calculation Unit offers a unified read and write access over the concatenated RF, IOF and DM space, that is, over the Unified Memory (UM) space. <br>
 Loads and stores operate in the UM space. They use the DACU in order to translate the Unified Memory address into a RF, IOF or DM address. <br>
 The DACU takes requests to read or write into UM space, translates the UM address into RF, IOF or DM address, and transparently places requests to read or write the specific hardware resource (RF, IOF or DM) that corresponds to the given UM address. <br>
</dl><dl compact><dt><b>
Reading DACU</b><dd>
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<img src="pavr_hwres_dacu_01.gif" alt="pavr_hwres_dacu_01.gif">
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<br>
 DACU read <b>requests</b>: <ul>
<li> pavr_s5_x_dacurd_rq <br>
 Needed by loads from address given by X pointer register. <li> pavr_s5_y_dacurd_rq <br>
 Needed by loads from address given by Y pointer register. <li> pavr_s5_z_dacurd_rq <br>
 Needed by loads from address given by Z pointer register. <li> pavr_s5_sp_dacurd_rq <br>
 Needed by POP instruction. <li> pavr_s5_k16_dacurd_rq <br>
 Needed by LDS instruction. <br>
 If the controller has more than 64KB of Data Memory, the Unified Memory address is built by concatenating the RAMPD with the 16 bit constant. <li> pavr_s5_pchi8_dacurd_rq <br>
 The higher 8 bits of the PC are loaded from the stack. <br>
 Needed by RET and RETI instructions. <li> pavr_s51_pcmid8_dacurd_rq <br>
 The middle 8 bits of the PC are loaded from the stack. <br>
 Needed by RET and RETI instructions. <li> pavr_s52_pclo8_dacurd_rq <br>
 The lower 8 bits of the PC are loaded from the stack. <br>
 Needed by RET and RETI instructions. </ul>
<br>
 As a response to read requests, the DACU places read <b>requests</b> to RF, IOF or DM: <ul>
<li> pavr_s5_dacu_rfrd1_rq <li> pavr_s5_dacu_iof_rq <li> pavr_s5_dacu_dmrd_rq </ul>
</dl><dl compact><dt><b>
Writing DACU</b><dd>
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<img src="pavr_hwres_dacu_02.gif" alt="pavr_hwres_dacu_02.gif">
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<br>
 DACU write <b>requests</b>: <ul>
<li> pavr_s5_x_dacuwr_rq <br>
 Needed by stores to address given by X pointer register. <li> pavr_s5_y_dacuwr_rq <br>
 Needed by stores to address given by Y pointer register. <li> pavr_s5_z_dacuwr_rq <br>
 Needed by stores to address given by Z pointer register. <li> pavr_s5_sp_dacuwr_rq <br>
 Needed by PUSH instruction. <br>
 <li> pavr_s5_k16_dacuwr_rq <br>
 Needed by STS instruction. <br>
 If the controller has more than 64KB of Data Memory, the Unified Memory address is built by concatenating the RAMPD with the 16 bit constant. <li> pavr_s5_pclo8_dacuwr_rq <br>
 The lower 8 bits of the PC are stored on the stack. <br>
 Needed by CALL family instructions (CALL, RCALL, ICALL, EICALL, implicit interrupt CALL). <li> pavr_s51_pcmid8_dacuwr_rq <br>
 The middle 8 bits of the PC are stored on the stack. <br>
 Needed by CALL family instructions. <li> pavr_s52_pchi8_dacuwr_rq <br>
 The higher 8 bits of the PC are stored on the stack. <br>
 Needed by CALL family instructions. </ul>
<br>
 As a response to write requests, the DACU places write <b>requests</b> to RF, IOF or DM, and BPU: <ul>
<li> pavr_s5_dacu_rfwr_rq <li> pavr_s5_dacu_iof_rq <li> pavr_s5_dacu_dmwr_rq <li> pavr_s5_dacust_bpr0wr_rq </ul>
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