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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1"> <title>Data Memory</title> <link href="doxygen.css" rel="stylesheet" type="text/css"> </head><body> <!-- Generated by Doxygen 1.2.16 --> <center> <a class="qindex" href="main.html">Main Page</a> <a class="qindex" href="modules.html">Modules</a> <a class="qindex" href="pages.html">Related Pages</a> </center> <hr><h1>Data Memory<br> <small> [<a class="el" href="group__pavr__hwres.html">Hardware resources</a>]</small> </h1><table border=0 cellpadding=0 cellspacing=0> </table> <dl compact><dt><b> Data Memory connectivity</b><dd> <br> <div align="center"> <img src="pavr_hwres_dm_01.gif" alt="pavr_hwres_dm_01.gif"> </div> <br> The Data Memory is a single port RAM. <br> That port provides both read and write DM accesses. <br> The DM is organized on bytes, and has the length set by a constant in the constants definition file (`pavr-constants.vhd'). <br> <br> </dl><dl compact><dt><b> Requests to DM</b><dd> Requests to access DM come only from the DACU: <br> <ul> <li>pavr_s5_dacu_dmrd_rq <br> <li>pavr_s5_dacu_dmwr_rq <br> <br> </ul> </dl><hr><address align="right"><small>Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by <a href="http://www.doxygen.org/index.html"> <img src="doxygen.png" alt="doxygen" align="middle" border=0 width=110 height=53></a>1.2.16 </small></address> </body> </html>