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<hr><h1>Port A<br>
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[<a class="el" href="group__pavr__hwres__iof__perif.html">Peripherals</a>]</small>
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Port A structure</b><dd>
The port A offers 8 bidirectional general purpose IO lines. <br>
 Lines 0 and 1 also have alternate functions: <ul>
<li> line 0 can be used as <a class="el" href="group__pavr__hwres__iof__perif__int0.html">external interrupt 0</a> input <li> line 1 can be used as <a class="el" href="group__pavr__hwres__iof__perif__t0.html">timer 0</a> clock input. </ul>
<br>
 Port A is managed through 3 IO File locations: <b>PORTA</b>, <b>DDRA</b> and <b>PINA</b>. <br>
 <b>DDRA</b> sets each pin's direction: DDRA(i)=0 means that line i is input, DDRA(i)=1 means that line i is output. <br>
 When writing a value to the port, that value goes into <b>PORTA</b>. If DDRA configures the corresponding lines as outputs, the contents of PORTA will be available on external pins. However, if DDRA configures the lines as inputs (DDRA(i)=0), then: <ul>
<li> if PORTA(i)=0, the line i is `pure' input (High Z). <br>
 <li> if PORTA(i)=1, the line i is an input weakly pulled high. <br>
 </ul>
<b>PINA</b> reads the physical value of external lines, rather than PORTA. <br>
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Port A schematics</b><dd>
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