Subversion Repositories pcie_mini_axi4s_wb

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-- Project name: pcie_mini_axi4s_wb, device top level file, EXAMPLE DESIGN
-- This is an example device top level file, where the pcie_mini_axi4s_wb is instantiated.
-- Functions: PCIe endpoint, a register block, 2 LED outputs.
--
-- YOU don't need this file in your own custom design !!! This file is only demonstration.
--
-- Engineer: Istvan Nagy, buenoshun@gmail.com
-- 
-- Create Date:    10/10/2019
-- Modify date:    10/10/2019
-- Design Name:    example_device_top encapsulating pcie_mini_axi4s_wb
-- Version:        1.0
-- Tool versions: Vivado 2019.1
--
-- Target Devices: Xilinx usc+ FPGAs. 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--entity header ----------------------------------------------------------------
entity example_device_top is
Port ( 
			 pci_exp_txp             : out std_logic;
			 pci_exp_txn             : out std_logic;
			 pci_exp_rxp             : in  std_logic;
			 pci_exp_rxn             : in  std_logic;	 
			 sys_clk_n                 : in  std_logic;
			 sys_clk_p                 : in  std_logic;
			 sys_reset_n             : in  std_logic;
			 debug_pins            : out std_logic_vector(31 downto 0);
			 scan_pins            : in std_logic_vector(31 downto 0);
			 led_out_1             : out std_logic;
			 led_out_2             : out std_logic
);
end example_device_top;
--architecture start ------------------------------------------------------------
architecture Behavioral of example_device_top is
 
-- INTERNAL SIGNALS -------------------------------------------------------------
	SIGNAL dummy0: std_logic;
	SIGNAL dummy1: std_logic_VECTOR(6 DOWNTO 0);
	SIGNAL   	 pcie_bar0_wb_data_o : std_logic_vector(31 downto 0); 				
	SIGNAL   	 pcie_bar0_wb_data_i : std_logic_vector(31 downto 0);				
	SIGNAL   	 pcie_bar0_wb_addr_o : std_logic_vector(27 downto 0);				
	SIGNAL   	 pcie_bar0_wb_cyc_o : std_logic;				
	SIGNAL   	 pcie_bar0_wb_stb_o : std_logic;				
	SIGNAL   	 pcie_bar0_wb_wr_o : std_logic;				
	SIGNAL   	 pcie_bar0_wb_ack_i : std_logic;				
	SIGNAL   	 pcie_bar0_wb_clk_o : std_logic; --62.5MHz				
	SIGNAL   	 pcie_bar0_wb_sel_o : std_logic_vector(3 downto 0);			 	
	SIGNAL   	 pcie_irq : std_logic;				
	SIGNAL   	 pcie_msi_enabled : std_logic;				
	SIGNAL   	 pcie_resetout  : std_logic;				
	SIGNAL   	 register_one : std_logic_vector(31 downto 0); 
	SIGNAL   	 register_two : std_logic_vector(31 downto 0); 
	SIGNAL   	 register_three : std_logic_vector(31 downto 0); 
	SIGNAL   	 register_four : std_logic_vector(31 downto 0); 
	SIGNAL   	 regxx_scratchpad : std_logic_vector(31 downto 0); 
	SIGNAL   	 scan_pins_latched1 : std_logic_vector(31 downto 0); 
	SIGNAL   	 scan_pins_latched2 : std_logic_vector(31 downto 0); 
	SIGNAL     wb_config_state :  std_logic_vector(7 downto 0); 
	SIGNAL     ACK_copy : std_logic;	
 
 
 
--------- COMPONENT DECLARATIONS (introducing the IPs) --------------------------
COMPONENT pcie_mini_axi4s_wb 
  PORT ( --FPGA PINS(EXTERNAL):
			 pci_exp_txp             : out std_logic;
			 pci_exp_txn             : out std_logic;
			 pci_exp_rxp             : in  std_logic;
			 pci_exp_rxn             : in  std_logic;	 
			 sys_clk_n                 : in  std_logic;
			 sys_clk_p                 : in  std_logic;
			 sys_reset_n             : in  std_logic;			 
			 --ON CHIP PORTS:
			 --DATA BUS for BAR0 (wishbone):
			 pcie_bar0_wb_data_o : out std_logic_vector(31 downto 0); 
			 pcie_bar0_wb_data_i : in std_logic_vector(31 downto 0);
			 pcie_bar0_wb_addr_o : out std_logic_vector(27 downto 0);
			 pcie_bar0_wb_cyc_o : out std_logic;
			 pcie_bar0_wb_stb_o : out std_logic;
			 pcie_bar0_wb_wr_o : out std_logic;
			 pcie_bar0_wb_ack_i : in std_logic;
			 pcie_bar0_wb_clk_o : out std_logic; --62.5MHz		
			 pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0);			 		 		 
			 --OTHER:
			 pcie_irq : in std_logic;
			 pcie_msi_enabled : out std_logic;	-- added to monitor if MSI interrupt is enabled
			 pcie_resetout  : out std_logic --active high
			);
END COMPONENT;
 
 
--architecture body start -------------------------------------------------------
begin
--------- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------
Inst_pcieaxiwbtop: pcie_mini_axi4s_wb 
  PORT MAP (
	 pci_exp_txp      	 => 	 pci_exp_txp,
	 pci_exp_txn      	 => 	 pci_exp_txn,
     pci_exp_rxp     	 => 	 pci_exp_rxp,
     pci_exp_rxn     	 => 	 pci_exp_rxn,
	 sys_clk_n         	 => 	 sys_clk_n,
	 sys_clk_p         	 => 	 sys_clk_p,
	 sys_reset_n     	 => 	 sys_reset_n,
	 pcie_bar0_wb_data_o 	 => 	 pcie_bar0_wb_data_o,
	 pcie_bar0_wb_data_i 	 => 	 pcie_bar0_wb_data_i,
	 pcie_bar0_wb_addr_o 	 => 	 pcie_bar0_wb_addr_o,
	 pcie_bar0_wb_cyc_o 	 => 	 pcie_bar0_wb_cyc_o,
	 pcie_bar0_wb_stb_o 	 => 	 pcie_bar0_wb_stb_o,
	 pcie_bar0_wb_wr_o 	 => 	 pcie_bar0_wb_wr_o,
	 pcie_bar0_wb_ack_i 	 => 	 pcie_bar0_wb_ack_i,
	 pcie_bar0_wb_clk_o 	 => 	 pcie_bar0_wb_clk_o,
	 pcie_bar0_wb_sel_o 	 => 	 pcie_bar0_wb_sel_o,
	 pcie_irq 	 => 	 pcie_irq,
	 pcie_msi_enabled 	 => 	 pcie_msi_enabled,
	 pcie_resetout  	 => 	 pcie_resetout  		
  );
 
 
-- local Logic ------------------------------------------------------------------
debug_pins <= register_one; --check register content with TopJtag_Probe.
led_out_1 <= register_one(1);
led_out_2 <= register_one(2);
 
-- WISHB/SMB REGISTER SET 
wishbone: process (pcie_resetout , pcie_bar0_wb_clk_o) is
	begin
	if (pcie_resetout  ='0') then 
		--DAT_R(7 downto 0) <= (others => '0'); 
		register_one  <=  (OTHERS => '0');
		register_two  <=  (OTHERS => '0');
		register_three <=   (OTHERS => '0');
		register_four <=  (OTHERS => '0');
		wb_config_state  <=  (OTHERS => '0');
		regxx_scratchpad <=  (OTHERS => '0');	
		scan_pins_latched1 <=  (OTHERS => '0');
		scan_pins_latched2 <=  (OTHERS => '0'); 
		pcie_bar0_wb_data_i <= (OTHERS => '0');
	else
		if (pcie_bar0_wb_clk_o'event and pcie_bar0_wb_clk_o = '1') then
		  scan_pins_latched1 <= scan_pins;
		  scan_pins_latched2 <= scan_pins_latched1;
 
			 case ( wb_config_state ) is
 
			 --********** IDLE STATE  **********
			 when "00000000" =>   --state 0    
				--WAIT FOR WISHBONE TRANSACTION:
				pcie_bar0_wb_ack_i <= '0';
				ACK_copy <= '0';						
				--writes:
				if (pcie_bar0_wb_cyc_o = '1' and pcie_bar0_wb_wr_o = '1' and ACK_copy='0') then 
					wb_config_state <= "00001001";
				--reads:
				elsif (pcie_bar0_wb_cyc_o = '1' and pcie_bar0_wb_wr_o = '0' and ACK_copy='0')	then --read
					wb_config_state <= "00001010";
				end if;
 
			 --********** write STATE ********** 
			 when "00001001" =>   --state 1
				  wb_config_state <= "00000000"; --no wait states, go back to idle
				  pcie_bar0_wb_ack_i  <= '1';
				  ACK_copy <= '1';
					case (pcie_bar0_wb_addr_o(7 downto 0)) is				
						when X"00" => 		register_one  <=   pcie_bar0_wb_data_o(31 downto 0);
						when X"01" => 		register_two  <=   pcie_bar0_wb_data_o(31 downto 0);
						when X"02" => 		register_three <=   pcie_bar0_wb_data_o(31 downto 0);
						when X"03" => 		register_four <=   pcie_bar0_wb_data_o(31 downto 0);
						when others => 		regxx_scratchpad	 <=   pcie_bar0_wb_data_o(31 downto 0);
					end case; 				
 
 
			 --********** read STATE **********
			 when "00001010" =>   --state 2: registers read-out
				  wb_config_state <= "00000000"; --no wait states, go back to idle
				  pcie_bar0_wb_ack_i  <= '1';
				  ACK_copy <= '1';
					case (pcie_bar0_wb_addr_o(7 downto 0)) is					
						when X"00" => 		pcie_bar0_wb_data_i(31 downto 0) <=  	register_one  ;
						when X"01" => 		pcie_bar0_wb_data_i(31 downto 0) <=  	register_two  ; 
						when X"02" => 		pcie_bar0_wb_data_i(31 downto 0) <=  	register_three ;
						when X"03" => 		pcie_bar0_wb_data_i(31 downto 0) <=  	register_four ;
						when X"04" => 		pcie_bar0_wb_data_i(31 downto 0) <=  	scan_pins_latched2 ;
						when others => 		pcie_bar0_wb_data_i(31 downto 0) <=  	regxx_scratchpad ;
					end case; 					
 
			 when others => --error state
					 wb_config_state <= "00000000"; --go to state 0
			 end case; 
 
		end if;
	end if;
end process wishbone;	
 
 
 
--end file ----------------------------------------------------------------------
end Behavioral;