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[/] [pcie_mini_axi4s_wb/] [trunk/] [rtl/] [pcie_axi4s2trn_wrapper.vhd] - Rev 2
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------------------------------------------------------------------------------------ -- AXI4STREAM TO TRN WRAPPER FOR PCIE -- WRITTEN BY: ISTVAN NAGY, 2019 10 03 -- --THIS IS A WRAPPER FILE FOR CONENCTING THE AXI4STREAM BASED NEW XILINX PCIE-EP-IP --TO THE OLD PCIE_MINI PROJECT THAT EXPECTS THE PCIE EP IP TO HAVE A TRN INTERFACE. --LOGIC: AN AXI4STREAM INTERFACE, A TRN INTERFACE AND AN AXI4 DESCRIPTOR HANDLER. -- --Example design is 1-lane 5Gbps, status and eye capture ports enabled, --device used was Ultrascale+ xcku3p-ffva676-3-e -- Usage: -- Thius file is a wrapper for converting the axi4s interface of the new Ultrascal+ -- FPGA PCIE endpoint IP, to TRN, that works with the pcie_mini logic. The pcie_mini -- is also modified to implement the new header encoding, while this file is just -- for the bit timing signals conversion. --How this works: from UG672-appendix-J the TRN-AXI4S bit signal conversion/migration. --AXI4S does not provide original TLP header, only AXI4s header, handled in other file. -- naming: m_axis_cq = TRN_RX, while s_axis_cc = TRN_RX, on completion EP interface. ------------------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --entity header ---------------------------------------------------------------- entity pcie is generic ( TL_TX_RAM_RADDR_LATENCY : integer := 0; TL_TX_RAM_RDATA_LATENCY : integer := 2; TL_RX_RAM_RADDR_LATENCY : integer := 0; TL_RX_RAM_RDATA_LATENCY : integer := 2; TL_RX_RAM_WRITE_LATENCY : integer := 0; VC0_TX_LASTPACKET : integer := 14; VC0_RX_RAM_LIMIT : bit_vector := x"7FF"; VC0_TOTAL_CREDITS_PH : integer := 32; VC0_TOTAL_CREDITS_PD : integer := 211; VC0_TOTAL_CREDITS_NPH : integer := 8; VC0_TOTAL_CREDITS_CH : integer := 40; VC0_TOTAL_CREDITS_CD : integer := 211; VC0_CPL_INFINITE : boolean := TRUE; BAR0 : bit_vector := x"F0000000"; BAR1 : bit_vector := x"00000000"; BAR2 : bit_vector := x"00000000"; BAR3 : bit_vector := x"00000000"; BAR4 : bit_vector := x"00000000"; BAR5 : bit_vector := x"00000000"; EXPANSION_ROM : bit_vector := "0000000000000000000000"; DISABLE_BAR_FILTERING : boolean := FALSE; DISABLE_ID_CHECK : boolean := FALSE; TL_TFC_DISABLE : boolean := FALSE; TL_TX_CHECKS_DISABLE : boolean := FALSE; USR_CFG : boolean := FALSE; USR_EXT_CFG : boolean := FALSE; DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2; CLASS_CODE : bit_vector := x"068000"; CARDBUS_CIS_POINTER : bit_vector := x"00000000"; PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1"; PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"1"; PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE; PCIE_CAP_INT_MSG_NUM : bit_vector := "00000"; DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0; DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE; DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7; DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7; SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE; SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE; SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE; DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE; LINK_CAP_ASPM_SUPPORT : integer := 1; LINK_CAP_L0S_EXIT_LATENCY : integer := 7; LINK_CAP_L1_EXIT_LATENCY : integer := 7; LL_ACK_TIMEOUT : bit_vector := x"0000"; LL_ACK_TIMEOUT_EN : boolean := FALSE; LL_REPLAY_TIMEOUT : bit_vector := x"0000"; LL_REPLAY_TIMEOUT_EN : boolean := FALSE; MSI_CAP_MULTIMSGCAP : integer := 0; MSI_CAP_MULTIMSG_EXTENSION : integer := 0; LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE; PLM_AUTO_CONFIG : boolean := FALSE; FAST_TRAIN : boolean := FALSE; ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE; DISABLE_SCRAMBLING : boolean := FALSE; PM_CAP_VERSION : integer := 3; PM_CAP_PME_CLOCK : boolean := FALSE; PM_CAP_DSI : boolean := FALSE; PM_CAP_AUXCURRENT : integer := 0; PM_CAP_D1SUPPORT : boolean := TRUE; PM_CAP_D2SUPPORT : boolean := TRUE; PM_CAP_PMESUPPORT : bit_vector := x"0F"; PM_DATA0 : bit_vector := x"04"; PM_DATA_SCALE0 : bit_vector := x"0"; PM_DATA1 : bit_vector := x"00"; PM_DATA_SCALE1 : bit_vector := x"0"; PM_DATA2 : bit_vector := x"00"; PM_DATA_SCALE2 : bit_vector := x"0"; PM_DATA3 : bit_vector := x"00"; PM_DATA_SCALE3 : bit_vector := x"0"; PM_DATA4 : bit_vector := x"04"; PM_DATA_SCALE4 : bit_vector := x"0"; PM_DATA5 : bit_vector := x"00"; PM_DATA_SCALE5 : bit_vector := x"0"; PM_DATA6 : bit_vector := x"00"; PM_DATA_SCALE6 : bit_vector := x"0"; PM_DATA7 : bit_vector := x"00"; PM_DATA_SCALE7 : bit_vector := x"0"; PCIE_GENERIC : bit_vector := "000011101111"; GTP_SEL : integer := 0; CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE"; CFG_DEV_ID : std_logic_vector(15 downto 0) := x"ABCD"; CFG_REV_ID : std_logic_vector(7 downto 0) := x"00"; CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE"; CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234"; REF_CLK_FREQ : integer := 0 ); port ( -- PCI Express Fabric Interface pci_exp_txp : out std_logic; pci_exp_txn : out std_logic; pci_exp_rxp : in std_logic; pci_exp_rxn : in std_logic; -- Transaction (TRN) Interface trn_lnk_up_n : out std_logic; -- Tx trn_td : in std_logic_vector(63 downto 0); trn_tsof_n : in std_logic; trn_teof_n : in std_logic; trn_tsrc_rdy_n : in std_logic; trn_tdst_rdy_n : out std_logic; trn_terr_drop_n : out std_logic; trn_tsrc_dsc_n : in std_logic; trn_terrfwd_n : in std_logic; trn_tbuf_av : out std_logic_vector(5 downto 0); trn_tstr_n : in std_logic; trn_tcfg_req_n : out std_logic; trn_tcfg_gnt_n : in std_logic; --trn_trem_n : in std_logic; --this might be needed for correct number of bytes transfer ????????? -- Rx trn_rd : out std_logic_vector(63 downto 0); trn_rsof_n : out std_logic; trn_reof_n : out std_logic; trn_rsrc_rdy_n : out std_logic; trn_rsrc_dsc_n : out std_logic; trn_rdst_rdy_n : in std_logic; trn_rerrfwd_n : out std_logic; trn_rnp_ok_n : in std_logic; trn_rbar_hit_n : out std_logic_vector(6 downto 0); trn_fc_sel : in std_logic_vector(2 downto 0); trn_fc_nph : out std_logic_vector(7 downto 0); trn_fc_npd : out std_logic_vector(11 downto 0); trn_fc_ph : out std_logic_vector(7 downto 0); trn_fc_pd : out std_logic_vector(11 downto 0); trn_fc_cplh : out std_logic_vector(7 downto 0); trn_fc_cpld : out std_logic_vector(11 downto 0); -- Host (CFG) Interface cfg_do : out std_logic_vector(31 downto 0); cfg_rd_wr_done_n : out std_logic; cfg_dwaddr : in std_logic_vector(9 downto 0); cfg_rd_en_n : in std_logic; cfg_err_ur_n : in std_logic; cfg_err_cor_n : in std_logic; cfg_err_ecrc_n : in std_logic; cfg_err_cpl_timeout_n : in std_logic; cfg_err_cpl_abort_n : in std_logic; cfg_err_posted_n : in std_logic; cfg_err_locked_n : in std_logic; cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0); cfg_err_cpl_rdy_n : out std_logic; cfg_interrupt_n : in std_logic; cfg_interrupt_rdy_n : out std_logic; cfg_interrupt_assert_n : in std_logic; cfg_interrupt_do : out std_logic_vector(7 downto 0); cfg_interrupt_di : in std_logic_vector(7 downto 0); cfg_interrupt_mmenable : out std_logic_vector(2 downto 0); cfg_interrupt_msienable : out std_logic; cfg_turnoff_ok_n : in std_logic; cfg_to_turnoff_n : out std_logic; cfg_pm_wake_n : in std_logic; cfg_pcie_link_state_n : out std_logic_vector(2 downto 0); --new encoding: 1xx=down, x00=no_receivers, x01=linktraining, x10=DLLinit, 011=linkUP. Spartan6 encode was different. cfg_trn_pending_n : in std_logic; cfg_dsn : in std_logic_vector(63 downto 0); cfg_bus_number : out std_logic_vector(7 downto 0); cfg_device_number : out std_logic_vector(4 downto 0); cfg_function_number : out std_logic_vector(2 downto 0); cfg_status : out std_logic_vector(15 downto 0); cfg_command : out std_logic_vector(15 downto 0); cfg_dstatus : out std_logic_vector(15 downto 0); cfg_dcommand : out std_logic_vector(15 downto 0); cfg_lstatus : out std_logic_vector(15 downto 0); cfg_lcommand : out std_logic_vector(15 downto 0); -- System Interface sys_clk : in std_logic; --ref clock oscillator 100mhz sys_clk2 : in std_logic; sys_reset_n : in std_logic; trn_clk : out std_logic; --parallel bus clock 52/125mhz trn_reset_n : out std_logic; received_hot_reset : out std_logic ); end pcie; architecture rtl of pcie is --attribute CORE_GENERATION_INFO : STRING; --attribute CORE_GENERATION_INFO of rtl : architecture is -- "pcie,s6_pcie_v1_2,{TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=14,VC0_RX_RAM_LIMIT=7FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=211,VC0_TOTAL_CREDITS_NPH=8,VC0_TOTAL_CREDITS_CH=40,VC0_TOTAL_CREDITS_CD=211,VC0_CPL_INFINITE=TRUE,BAR0=F0000000,BAR1=00000000,BAR2=00000000,BAR3=00000000,BAR4=00000000,BAR5=00000000,EXPANSION_ROM=000000,USR_CFG=FALSE,USR_EXT_CFG=FALSE,DEV_CAP_MAX_PAYLOAD_SUPPORTED=2,CLASS_CODE=068000,CARDBUS_CIS_POINTER=00000000,PCIE_CAP_CAPABILITY_VERSION=1,PCIE_CAP_DEVICE_PORT_TYPE=1,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,DEV_CAP_ENDPOINT_L0S_LATENCY=7,DEV_CAP_ENDPOINT_L1_LATENCY=7,LINK_CAP_ASPM_SUPPORT=1,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,LINK_STATUS_SLOT_CLOCK_CONFIG=FALSE,ENABLE_RX_TD_ECRC_TRIM=FALSE,DISABLE_SCRAMBLING=FALSE,PM_CAP_DSI=FALSE,PM_CAP_D1SUPPORT=TRUE,PM_CAP_D2SUPPORT=TRUE,PM_CAP_PMESUPPORT=0F,PM_DATA0=04,PM_DATA_SCALE0=0,PM_DATA1=00,PM_DATA_SCALE1=0,PM_DATA2=00,PM_DATA_SCALE2=0,PM_DATA3=00,PM_DATA_SCALE3=0,PM_DATA4=04,PM_DATA_SCALE4=0,PM_DATA5=00,PM_DATA_SCALE5=0,PM_DATA6=00,PM_DATA_SCALE6=0,PM_DATA7=00,PM_DATA_SCALE7=0,PCIE_GENERIC=000010101111,GTP_SEL=0,CFG_VEN_ID=10EE,CFG_DEV_ID=ABCD,CFG_REV_ID=00,CFG_SUBSYS_VEN_ID=10EE,CFG_SUBSYS_ID=1234,REF_CLK_FREQ=0}"; -- INTERNAL SIGNALS ------------------------------------------------------------- SIGNAL pl_gen2_upstream_prefer_deemph : std_logic; SIGNAL pl_redo_eq : std_logic; SIGNAL pl_redo_eq_speed : std_logic; SIGNAL s_axis_cc_tdata : std_logic_vector(63 downto 0); SIGNAL s_axis_rq_tdata : std_logic_vector(63 downto 0); SIGNAL s_axis_cc_tuser : std_logic_vector(32 downto 0); SIGNAL s_axis_rq_tlast : std_logic; SIGNAL s_axis_cc_tlast : std_logic; SIGNAL pcie_cq_np_req : std_logic_vector(1 downto 0); SIGNAL s_axis_rq_tuser : std_logic_vector(61 downto 0); SIGNAL s_axis_cc_tkeep : std_logic_vector(1 downto 0); SIGNAL s_axis_rq_tkeep : std_logic_vector(1 downto 0); SIGNAL s_axis_cc_tvalid : std_logic; SIGNAL s_axis_rq_tvalid : std_logic; SIGNAL m_axis_cq_tready : std_logic; SIGNAL m_axis_rc_tready : std_logic; SIGNAL cfg_mgmt_addr : std_logic_vector(9 downto 0); SIGNAL cfg_mgmt_function_number : std_logic_vector(7 downto 0); SIGNAL cfg_mgmt_write : std_logic; SIGNAL cfg_mgmt_write_data : std_logic_vector(31 downto 0); SIGNAL cfg_mgmt_byte_enable : std_logic_vector(3 downto 0); SIGNAL cfg_mgmt_read : std_logic; SIGNAL cfg_mgmt_debug_access : std_logic; SIGNAL cfg_msg_transmit : std_logic; SIGNAL cfg_msg_transmit_type : std_logic_vector(2 downto 0); SIGNAL cfg_msg_transmit_data : std_logic_vector(31 downto 0); SIGNAL cfg_fc_sel : std_logic_vector(2 downto 0); SIGNAL cfg_hot_reset_in : std_logic; SIGNAL cfg_config_space_enable : std_logic; --SIGNAL cfg_dsn : std_logic_vector(63 downto 0); SIGNAL cfg_dev_id_pf0 : std_logic_vector(15 downto 0); SIGNAL cfg_dev_id_pf1 : std_logic_vector(15 downto 0); SIGNAL cfg_dev_id_pf2 : std_logic_vector(15 downto 0); SIGNAL cfg_dev_id_pf3 : std_logic_vector(15 downto 0); SIGNAL cfg_vend_id : std_logic_vector(15 downto 0); SIGNAL cfg_rev_id_pf0 : std_logic_vector(7 downto 0); SIGNAL cfg_rev_id_pf1 : std_logic_vector(7 downto 0); SIGNAL cfg_rev_id_pf2 : std_logic_vector(7 downto 0); SIGNAL cfg_rev_id_pf3 : std_logic_vector(7 downto 0); SIGNAL cfg_subsys_id_pf0 : std_logic_vector(15 downto 0); SIGNAL cfg_subsys_id_pf1 : std_logic_vector(15 downto 0); SIGNAL cfg_subsys_id_pf2 : std_logic_vector(15 downto 0); SIGNAL cfg_subsys_id_pf3 : std_logic_vector(15 downto 0); SIGNAL cfg_subsys_vend_id : std_logic_vector(15 downto 0); SIGNAL cfg_ds_port_number : std_logic_vector(7 downto 0); SIGNAL cfg_ds_bus_number : std_logic_vector(7 downto 0); SIGNAL cfg_ds_device_number : std_logic_vector(4 downto 0); SIGNAL cfg_ds_function_number : std_logic_vector(2 downto 0); SIGNAL cfg_power_state_change_ack : std_logic; SIGNAL cfg_err_cor_in : std_logic; SIGNAL cfg_err_uncor_in : std_logic; SIGNAL cfg_flr_done : std_logic_vector(3 downto 0); SIGNAL cfg_req_pm_transition_l23_ready : std_logic; SIGNAL cfg_link_training_enable : std_logic; SIGNAL cfg_interrupt_int : std_logic_vector(3 downto 0); SIGNAL cfg_interrupt_pending : std_logic_vector(3 downto 0); SIGNAL cfg_interrupt_msi_int : std_logic_vector(31 downto 0); SIGNAL cfg_interrupt_msi_pending_status : std_logic_vector(31 downto 0); SIGNAL cfg_interrupt_msi_pending_status_function_num : std_logic_vector(1 downto 0); SIGNAL cfg_interrupt_msi_pending_status_data_enable : std_logic; SIGNAL cfg_interrupt_msi_select : std_logic_vector(1 downto 0); SIGNAL cfg_interrupt_msix_address : std_logic_vector(63 downto 0); SIGNAL cfg_interrupt_msix_data : std_logic_vector(31 downto 0); SIGNAL cfg_interrupt_msix_int : std_logic; SIGNAL cfg_interrupt_msix_vec_pending : std_logic_vector(1 downto 0); SIGNAL cfg_interrupt_msi_attr : std_logic_vector(2 downto 0); SIGNAL cfg_interrupt_msi_tph_present : std_logic; SIGNAL cfg_interrupt_msi_tph_type : std_logic_vector(1 downto 0); SIGNAL cfg_interrupt_msi_tph_st_tag : std_logic_vector(7 downto 0); SIGNAL cfg_interrupt_msi_function_number : std_logic_vector(7 downto 0); SIGNAL cfg_ext_read_data : std_logic_vector(31 downto 0); SIGNAL cfg_ext_read_data_valid : std_logic; SIGNAL cfg_vf_flr_func_num : std_logic_vector(7 downto 0); SIGNAL cfg_vf_flr_done : std_logic_VECTOR(0 DOWNTO 0); SIGNAL cfg_pm_aspm_l1_entry_reject : std_logic; SIGNAL cfg_pm_aspm_tx_l0s_entry_disable : std_logic; SIGNAL conf_req_type : std_logic_vector(1 downto 0); SIGNAL conf_req_reg_num : std_logic_vector(3 downto 0); SIGNAL conf_req_data : std_logic_vector(31 downto 0); SIGNAL conf_req_valid : std_logic; SIGNAL cap_gnt : std_logic; SIGNAL cap_rel : std_logic; SIGNAL sys_clk_gt : std_logic; SIGNAL ext_ch_gt_drpaddr : std_logic_vector(79 downto 0); SIGNAL ext_ch_gt_drpen : std_logic_vector(7 downto 0); SIGNAL ext_ch_gt_drpwe : std_logic_vector(7 downto 0); SIGNAL ext_ch_gt_drpdi : std_logic_vector(127 downto 0); SIGNAL drp_clk : std_logic; SIGNAL drp_en : std_logic; SIGNAL drp_we : std_logic; SIGNAL drp_addr : std_logic_vector(9 downto 0); SIGNAL drp_di : std_logic_vector(15 downto 0); SIGNAL gt_pcieuserratedone : std_logic_vector(7 downto 0); SIGNAL gt_loopback : std_logic_vector(23 downto 0); SIGNAL gt_txprbsforceerr : std_logic_vector(7 downto 0); SIGNAL gt_txinhibit : std_logic_vector(7 downto 0); SIGNAL gt_txprbssel : std_logic_vector(31 downto 0); SIGNAL gt_rxprbssel : std_logic_vector(31 downto 0); SIGNAL gt_rxprbscntreset : std_logic_vector(7 downto 0); SIGNAL gt_dmonfiforeset : std_logic_vector(7 downto 0); SIGNAL gt_dmonitorclk : std_logic_vector(7 downto 0); SIGNAL gt_txpmareset : std_logic_vector(7 downto 0); SIGNAL gt_rxpmareset : std_logic_vector(7 downto 0); SIGNAL gt_txpcsreset : std_logic_vector(7 downto 0); SIGNAL gt_rxpcsreset : std_logic_vector(7 downto 0); SIGNAL gt_rxbufreset : std_logic_vector(7 downto 0); SIGNAL gt_rxcdrreset : std_logic_vector(7 downto 0); SIGNAL gt_rxdfelpmreset : std_logic_vector(7 downto 0); SIGNAL free_run_clock : std_logic; SIGNAL common_commands_in : std_logic_vector(25 downto 0); SIGNAL pipe_rx_0_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_1_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_2_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_3_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_4_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_5_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_6_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_7_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_8_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_9_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_10_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_11_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_12_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_13_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_14_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_rx_15_sigs : std_logic_vector(83 downto 0); SIGNAL ext_qpll0lock_out : std_logic_vector(1 downto 0); SIGNAL ext_qpll0outclk_out : std_logic_vector(1 downto 0); SIGNAL ext_qpll0outrefclk_out : std_logic_vector(1 downto 0); SIGNAL ext_qpll1lock_out : std_logic_vector(1 downto 0); SIGNAL ext_qpll1outclk_out : std_logic_vector(1 downto 0); SIGNAL ext_qpll1outrefclk_out : std_logic_vector(1 downto 0); SIGNAL qpll0lock_out : std_logic_vector(1 downto 0); SIGNAL qpll0outclk_out : std_logic_vector(1 downto 0); SIGNAL qpll0outrefclk_out : std_logic_vector(1 downto 0); SIGNAL qpll1lock_out : std_logic_vector(1 downto 0); SIGNAL qpll1outclk_out : std_logic_vector(1 downto 0); SIGNAL qpll1outrefclk_out : std_logic_vector(1 downto 0); SIGNAL pcierateqpllpd_out : std_logic_vector(15 downto 0); SIGNAL pcierateqpllreset_out : std_logic_vector(15 downto 0); SIGNAL bufgtce_out : std_logic_vector(7 downto 0); SIGNAL bufgtcemask_out : std_logic_vector(23 downto 0); SIGNAL bufgtdiv_out : std_logic_vector(71 downto 0); SIGNAL bufgtreset_out : std_logic_vector(7 downto 0); SIGNAL bufgtrstmask_out : std_logic_vector(23 downto 0); SIGNAL cplllock_out : std_logic_vector(7 downto 0); SIGNAL dmonitorout_out : std_logic_vector(127 downto 0); SIGNAL gtpowergood_out : std_logic_vector(7 downto 0); SIGNAL pcierategen3_out : std_logic_vector(7 downto 0); SIGNAL pcierateidle_out : std_logic_vector(7 downto 0); SIGNAL pciesynctxsyncdone_out : std_logic_vector(7 downto 0); SIGNAL pcieusergen3rdy_out : std_logic_vector(7 downto 0); SIGNAL pcieuserphystatusrst_out : std_logic_vector(7 downto 0); SIGNAL pcieuserratestart_out : std_logic_vector(7 downto 0); SIGNAL phystatus_out : std_logic_vector(7 downto 0); SIGNAL rxbufstatus_out : std_logic_vector(23 downto 0); SIGNAL rxbyteisaligned_out : std_logic_vector(7 downto 0); SIGNAL rxbyterealign_out : std_logic_vector(7 downto 0); SIGNAL rxcdrlock_out : std_logic_vector(7 downto 0); SIGNAL rxclkcorcnt_out : std_logic_vector(15 downto 0); SIGNAL rxcommadet_out : std_logic_vector(7 downto 0); SIGNAL rxctrl0_out : std_logic_vector(127 downto 0); SIGNAL rxctrl1_out : std_logic_vector(127 downto 0); SIGNAL rxctrl2_out : std_logic_vector(63 downto 0); SIGNAL rxctrl3_out : std_logic_vector(63 downto 0); SIGNAL rxdata_out : std_logic_vector(1023 downto 0); SIGNAL rxdlysresetdone_out : std_logic_vector(7 downto 0); SIGNAL rxelecidle_out : std_logic_vector(7 downto 0); SIGNAL rxoutclk_out : std_logic_vector(7 downto 0); SIGNAL rxoutclkfabric_out : std_logic_vector(7 downto 0); SIGNAL rxoutclkpcs_out : std_logic_vector(7 downto 0); SIGNAL rxphaligndone_out : std_logic_vector(7 downto 0); SIGNAL rxpmaresetdone_out : std_logic_vector(7 downto 0); SIGNAL rxprbserr_out : std_logic_vector(7 downto 0); SIGNAL rxprbslocked_out : std_logic_vector(7 downto 0); SIGNAL rxratedone_out : std_logic_vector(7 downto 0); SIGNAL rxrecclkout_out : std_logic_vector(7 downto 0); SIGNAL rxresetdone_out : std_logic_vector(7 downto 0); SIGNAL rxstatus_out : std_logic_vector(23 downto 0); SIGNAL rxsyncdone_out : std_logic_vector(7 downto 0); SIGNAL rxvalid_out : std_logic_vector(7 downto 0); SIGNAL txdlysresetdone_out : std_logic_vector(7 downto 0); SIGNAL txoutclk_out : std_logic_vector(7 downto 0); SIGNAL txoutclkfabric_out : std_logic_vector(7 downto 0); SIGNAL txoutclkpcs_out : std_logic_vector(7 downto 0); SIGNAL txphaligndone_out : std_logic_vector(7 downto 0); SIGNAL txphinitdone_out : std_logic_vector(7 downto 0); SIGNAL txpmaresetdone_out : std_logic_vector(7 downto 0); SIGNAL txprgdivresetdone_out : std_logic_vector(7 downto 0); SIGNAL txresetdone_out : std_logic_vector(7 downto 0); SIGNAL txsyncdone_out : std_logic_vector(7 downto 0); SIGNAL txsyncout_out : std_logic_vector(7 downto 0); SIGNAL drprdy_out : std_logic_vector(7 downto 0); SIGNAL drpdo_out : std_logic_vector(127 downto 0); SIGNAL ext_phy_clk_pclk2_gt : std_logic; SIGNAL ext_phy_clk_int_clock : std_logic; SIGNAL ext_phy_clk_pclk : std_logic; SIGNAL ext_phy_clk_phy_pclk2 : std_logic; SIGNAL ext_phy_clk_phy_coreclk : std_logic; SIGNAL ext_phy_clk_phy_userclk : std_logic; SIGNAL ext_phy_clk_phy_mcapclk : std_logic; SIGNAL prst_clk : std_logic; SIGNAL pl_eq_in_progress : std_logic; SIGNAL pl_eq_phase : std_logic_vector(1 downto 0); SIGNAL pl_eq_mismatch : std_logic; SIGNAL pl_redo_eq_pending : std_logic; SIGNAL m_axis_cq_tdata : std_logic_vector(63 downto 0); SIGNAL m_axis_rc_tdata : std_logic_vector(63 downto 0); SIGNAL m_axis_cq_tuser : std_logic_vector(87 downto 0); SIGNAL m_axis_cq_tlast : std_logic; SIGNAL m_axis_rc_tlast : std_logic; SIGNAL pcie_cq_np_req_count : std_logic_vector(5 downto 0); SIGNAL m_axis_rc_tuser : std_logic_vector(74 downto 0); SIGNAL m_axis_cq_tkeep : std_logic_vector(1 downto 0); SIGNAL m_axis_rc_tkeep : std_logic_vector(1 downto 0); SIGNAL m_axis_cq_tvalid : std_logic; SIGNAL m_axis_rc_tvalid : std_logic; SIGNAL s_axis_cc_tready : std_logic_vector(3 downto 0); SIGNAL s_axis_rq_tready : std_logic_vector(3 downto 0); SIGNAL pcie_rq_seq_num0 : std_logic_vector(5 downto 0); SIGNAL pcie_rq_seq_num_vld0 : std_logic; SIGNAL pcie_rq_seq_num1 : std_logic_vector(5 downto 0); SIGNAL pcie_rq_seq_num_vld1 : std_logic; SIGNAL pcie_rq_tag0 : std_logic_vector(7 downto 0); SIGNAL pcie_rq_tag_vld0 : std_logic; SIGNAL pcie_rq_tag1 : std_logic_vector(7 downto 0); SIGNAL pcie_rq_tag_vld1 : std_logic; SIGNAL pcie_tfc_nph_av : std_logic_vector(3 downto 0); SIGNAL pcie_tfc_npd_av : std_logic_vector(3 downto 0); SIGNAL pcie_rq_tag_av : std_logic_vector(3 downto 0); SIGNAL cfg_mgmt_read_data : std_logic_vector(31 downto 0); SIGNAL cfg_mgmt_read_write_done : std_logic; SIGNAL cfg_phy_link_down : std_logic; SIGNAL cfg_phy_link_status : std_logic_vector(1 downto 0); SIGNAL cfg_negotiated_width : std_logic_vector(2 downto 0); SIGNAL cfg_current_speed : std_logic_vector(1 downto 0); SIGNAL cfg_max_payload : std_logic_vector(1 downto 0); SIGNAL cfg_max_read_req : std_logic_vector(2 downto 0); SIGNAL cfg_function_status : std_logic_vector(15 downto 0); SIGNAL cfg_function_power_state : std_logic_vector(11 downto 0); SIGNAL cfg_link_power_state : std_logic_vector(1 downto 0); SIGNAL cfg_err_cor_out : std_logic; SIGNAL cfg_err_nonfatal_out : std_logic; SIGNAL cfg_err_fatal_out : std_logic; SIGNAL cfg_local_error_valid : std_logic; SIGNAL cfg_local_error_out : std_logic_vector(4 downto 0); SIGNAL cfg_ltssm_state : std_logic_vector(5 downto 0); SIGNAL cfg_rx_pm_state : std_logic_vector(1 downto 0); SIGNAL cfg_tx_pm_state : std_logic_vector(1 downto 0); SIGNAL cfg_rcb_status : std_logic_vector(3 downto 0); SIGNAL cfg_obff_enable : std_logic_vector(1 downto 0); SIGNAL cfg_pl_status_change : std_logic; SIGNAL cfg_tph_requester_enable : std_logic_vector(3 downto 0); SIGNAL cfg_tph_st_mode : std_logic_vector(11 downto 0); SIGNAL cfg_msg_received : std_logic; SIGNAL cfg_msg_received_data : std_logic_vector(7 downto 0); SIGNAL cfg_msg_received_type : std_logic_vector(4 downto 0); SIGNAL cfg_msg_transmit_done : std_logic; SIGNAL cfg_fc_ph : std_logic_vector(7 downto 0); SIGNAL cfg_fc_pd : std_logic_vector(11 downto 0); SIGNAL cfg_fc_nph : std_logic_vector(7 downto 0); SIGNAL cfg_fc_npd : std_logic_vector(11 downto 0); SIGNAL cfg_fc_cplh : std_logic_vector(7 downto 0); SIGNAL cfg_fc_cpld : std_logic_vector(11 downto 0); SIGNAL cfg_hot_reset_out : std_logic; --SIGNAL cfg_bus_number : std_logic_vector(7 downto 0); SIGNAL cfg_power_state_change_interrupt : std_logic; SIGNAL cfg_flr_in_process : std_logic_vector(3 downto 0); SIGNAL cfg_interrupt_sent : std_logic; SIGNAL cfg_interrupt_msi_enable : std_logic_vector(3 downto 0); SIGNAL cfg_interrupt_msi_sent : std_logic; SIGNAL cfg_interrupt_msi_fail : std_logic; SIGNAL cfg_interrupt_msi_mmenable : std_logic_vector(11 downto 0); SIGNAL cfg_interrupt_msi_mask_update : std_logic; SIGNAL cfg_interrupt_msi_data : std_logic_vector(31 downto 0); SIGNAL cfg_interrupt_msix_enable : std_logic_vector(3 downto 0); SIGNAL cfg_interrupt_msix_mask : std_logic_vector(3 downto 0); SIGNAL cfg_interrupt_msix_vec_pending_status : std_logic; SIGNAL cfg_ext_read_received : std_logic; SIGNAL cfg_ext_write_received : std_logic; SIGNAL cfg_ext_register_number : std_logic_vector(9 downto 0); SIGNAL cfg_ext_function_number : std_logic_vector(7 downto 0); SIGNAL cfg_ext_write_data : std_logic_vector(31 downto 0); SIGNAL cfg_ext_write_byte_enable : std_logic_vector(3 downto 0); SIGNAL rbar_bar_size : std_logic_vector(5 downto 0); SIGNAL rbar_function_number : std_logic_vector(7 downto 0); SIGNAL rbar_write_enable_bar0 : std_logic; SIGNAL rbar_write_enable_bar1 : std_logic; SIGNAL rbar_write_enable_bar2 : std_logic; SIGNAL rbar_write_enable_bar3 : std_logic; SIGNAL rbar_write_enable_bar4 : std_logic; SIGNAL rbar_write_enable_bar5 : std_logic; SIGNAL cfg_vf_flr_in_process : std_logic_vector(251 downto 0); SIGNAL cfg_vf_status : std_logic_vector(503 downto 0); SIGNAL cfg_vf_power_state : std_logic_vector(755 downto 0); SIGNAL cfg_vf_tph_requester_enable : std_logic_vector(251 downto 0); SIGNAL cfg_vf_tph_st_mode : std_logic_vector(755 downto 0); SIGNAL cfg_interrupt_msix_vf_enable : std_logic_vector(251 downto 0); SIGNAL cfg_interrupt_msix_vf_mask : std_logic_vector(251 downto 0); SIGNAL conf_req_ready : std_logic; SIGNAL conf_resp_rdata : std_logic_vector(31 downto 0); SIGNAL conf_resp_valid : std_logic; SIGNAL cap_req : std_logic; SIGNAL mcap_design_switch : std_logic; SIGNAL user_clk : std_logic; SIGNAL core_clk : std_logic; SIGNAL gt_drp_clk : std_logic; SIGNAL user_reset : std_logic; SIGNAL user_lnk_up : std_logic; SIGNAL sys_clk_ce_out : std_logic; SIGNAL ext_ch_gt_drpclk : std_logic; SIGNAL ext_ch_gt_drprdy : std_logic_vector(7 downto 0); SIGNAL ext_ch_gt_drpdo : std_logic_vector(127 downto 0); SIGNAL drp_rdy : std_logic; SIGNAL drp_do : std_logic_vector(15 downto 0); SIGNAL gt_txelecidle : std_logic_vector(7 downto 0); SIGNAL gt_txresetdone : std_logic_vector(7 downto 0); SIGNAL gt_rxresetdone : std_logic_vector(7 downto 0); SIGNAL gt_rxpmaresetdone : std_logic_vector(7 downto 0); SIGNAL gt_txphaligndone : std_logic_vector(7 downto 0); SIGNAL gt_txphinitdone : std_logic_vector(7 downto 0); SIGNAL gt_txdlysresetdone : std_logic_vector(7 downto 0); SIGNAL gt_rxphaligndone : std_logic_vector(7 downto 0); SIGNAL gt_rxdlysresetdone : std_logic_vector(7 downto 0); SIGNAL gt_rxsyncdone : std_logic_vector(7 downto 0); SIGNAL gt_eyescandataerror : std_logic_vector(7 downto 0); SIGNAL gt_rxprbserr : std_logic_vector(7 downto 0); SIGNAL gt_dmonitorout : std_logic_vector(127 downto 0); SIGNAL gt_rxcommadet : std_logic_vector(7 downto 0); SIGNAL gt_phystatus : std_logic_vector(7 downto 0); SIGNAL gt_rxvalid : std_logic_vector(7 downto 0); SIGNAL gt_rxcdrlock : std_logic_vector(7 downto 0); SIGNAL gt_pcierateidle : std_logic_vector(7 downto 0); SIGNAL gt_pcieuserratestart : std_logic_vector(7 downto 0); SIGNAL gt_gtpowergood : std_logic_vector(7 downto 0); SIGNAL gt_cplllock : std_logic_vector(7 downto 0); SIGNAL gt_rxoutclk : std_logic_vector(7 downto 0); SIGNAL gt_rxrecclkout : std_logic_vector(7 downto 0); SIGNAL gt_qpll0lock : std_logic_vector(1 downto 0); SIGNAL gt_qpll1lock : std_logic_vector(1 downto 0); SIGNAL gt_rxstatus : std_logic_vector(23 downto 0); SIGNAL gt_rxbufstatus : std_logic_vector(23 downto 0); SIGNAL gt_bufgtdiv : std_logic_vector(8 downto 0); SIGNAL phy_txeq_ctrl : std_logic_vector(15 downto 0); SIGNAL phy_txeq_preset : std_logic_vector(31 downto 0); SIGNAL phy_rst_fsm : std_logic_vector(3 downto 0); SIGNAL phy_txeq_fsm : std_logic_vector(23 downto 0); SIGNAL phy_rxeq_fsm : std_logic_vector(23 downto 0); SIGNAL phy_rst_idle : std_logic; SIGNAL phy_rrst_n : std_logic; SIGNAL phy_prst_n : std_logic; SIGNAL gt_gen34_eios_det : std_logic_vector(7 downto 0); SIGNAL gt_txoutclk : std_logic_vector(7 downto 0); SIGNAL gt_txoutclkfabric : std_logic_vector(7 downto 0); SIGNAL gt_rxoutclkfabric : std_logic_vector(7 downto 0); SIGNAL gt_txoutclkpcs : std_logic_vector(7 downto 0); SIGNAL gt_rxoutclkpcs : std_logic_vector(7 downto 0); SIGNAL gt_txprogdivresetdone : std_logic_vector(7 downto 0); SIGNAL gt_txpmaresetdone : std_logic_vector(7 downto 0); SIGNAL gt_txsyncdone : std_logic_vector(7 downto 0); SIGNAL gt_rxprbslocked : std_logic_vector(7 downto 0); SIGNAL common_commands_out : std_logic_vector(25 downto 0); SIGNAL pipe_tx_0_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_1_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_2_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_3_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_4_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_5_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_6_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_7_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_8_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_9_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_10_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_11_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_12_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_13_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_14_sigs : std_logic_vector(83 downto 0); SIGNAL pipe_tx_15_sigs : std_logic_vector(83 downto 0); SIGNAL int_qpll0lock_out : std_logic_vector(1 downto 0); SIGNAL int_qpll0outrefclk_out : std_logic_vector(1 downto 0); SIGNAL int_qpll0outclk_out : std_logic_vector(1 downto 0); SIGNAL int_qpll1lock_out : std_logic_vector(1 downto 0); SIGNAL int_qpll1outrefclk_out : std_logic_vector(1 downto 0); SIGNAL int_qpll1outclk_out : std_logic_vector(1 downto 0); SIGNAL ext_qpllxrefclk : std_logic_vector(1 downto 0); SIGNAL ext_qpllxrate : std_logic_vector(5 downto 0); SIGNAL ext_qpllxrcalenb : std_logic; SIGNAL ext_qpll0pd : std_logic_vector(1 downto 0); SIGNAL ext_qpll0reset : std_logic_vector(1 downto 0); SIGNAL ext_qpll1pd : std_logic_vector(1 downto 0); SIGNAL ext_qpll1reset : std_logic_vector(1 downto 0); SIGNAL gtrefclk01_in : std_logic_vector(1 downto 0); SIGNAL gtrefclk00_in : std_logic_vector(1 downto 0); SIGNAL pcierateqpll0_in : std_logic_vector(5 downto 0); SIGNAL pcierateqpll1_in : std_logic_vector(5 downto 0); SIGNAL qpll0pd_in : std_logic_vector(1 downto 0); SIGNAL qpll0reset_in : std_logic_vector(1 downto 0); SIGNAL qpll1pd_in : std_logic_vector(1 downto 0); SIGNAL qpll1reset_in : std_logic_vector(1 downto 0); SIGNAL qpll0freqlock_in : std_logic_vector(7 downto 0); SIGNAL qpll1freqlock_in : std_logic_vector(7 downto 0); SIGNAL rcalenb_in : std_logic_vector(1 downto 0); SIGNAL txpisopd_in : std_logic_vector(7 downto 0); SIGNAL cpllfreqlock_in : std_logic_vector(7 downto 0); SIGNAL cpllpd_in : std_logic_vector(7 downto 0); SIGNAL cpllreset_in : std_logic_vector(7 downto 0); SIGNAL dmonfiforeset_in : std_logic_vector(7 downto 0); SIGNAL dmonitorclk_in : std_logic_vector(7 downto 0); SIGNAL eyescanreset_in : std_logic_vector(7 downto 0); SIGNAL gtrefclk0_in : std_logic_vector(7 downto 0); SIGNAL gtrxreset_in : std_logic_vector(7 downto 0); SIGNAL gttxreset_in : std_logic_vector(7 downto 0); SIGNAL gtwiz_reset_rx_done_in : std_logic; SIGNAL gtwiz_reset_tx_done_in : std_logic; SIGNAL gtwiz_userclk_rx_active_in : std_logic; SIGNAL gtwiz_userclk_tx_active_in : std_logic; SIGNAL loopback_in : std_logic_vector(23 downto 0); SIGNAL pcieeqrxeqadaptdone_in : std_logic_vector(7 downto 0); SIGNAL pcierstidle_in : std_logic_vector(7 downto 0); SIGNAL pciersttxsyncstart_in : std_logic_vector(7 downto 0); SIGNAL pcieuserratedone_in : std_logic_vector(7 downto 0); SIGNAL resetovrd_in : std_logic_vector(7 downto 0); SIGNAL rx8b10ben_in : std_logic_vector(7 downto 0); SIGNAL rxbufreset_in : std_logic_vector(7 downto 0); SIGNAL rxcdrfreqreset_in : std_logic_vector(7 downto 0); SIGNAL rxcdrhold_in : std_logic_vector(7 downto 0); SIGNAL rxcdrreset_in : std_logic_vector(7 downto 0); SIGNAL rxcommadeten_in : std_logic_vector(7 downto 0); SIGNAL rxdfeagchold_in : std_logic_vector(7 downto 0); SIGNAL rxdfecfokhold_in : std_logic_vector(7 downto 0); SIGNAL rxdfekhhold_in : std_logic_vector(7 downto 0); SIGNAL rxdfelfhold_in : std_logic_vector(7 downto 0); SIGNAL rxdfelpmreset_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap10hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap11hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap12hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap13hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap14hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap15hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap2hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap3hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap4hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap5hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap6hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap7hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap8hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfetap9hold_in : std_logic_vector(7 downto 0); SIGNAL rxdfeuthold_in : std_logic_vector(7 downto 0); SIGNAL rxdfevphold_in : std_logic_vector(7 downto 0); SIGNAL rxlpmen_in : std_logic_vector(7 downto 0); SIGNAL rxlpmgchold_in : std_logic_vector(7 downto 0); SIGNAL rxlpmhfhold_in : std_logic_vector(7 downto 0); SIGNAL rxlpmlfhold_in : std_logic_vector(7 downto 0); SIGNAL rxlpmoshold_in : std_logic_vector(7 downto 0); SIGNAL rxmcommaalignen_in : std_logic_vector(7 downto 0); SIGNAL rxoshold_in : std_logic_vector(7 downto 0); SIGNAL rxpcommaalignen_in : std_logic_vector(7 downto 0); SIGNAL rxpcsreset_in : std_logic_vector(7 downto 0); SIGNAL rxpd_in : std_logic_vector(15 downto 0); SIGNAL rxpmareset_in : std_logic_vector(7 downto 0); SIGNAL rxpolarity_in : std_logic_vector(7 downto 0); SIGNAL rxprbscntreset_in : std_logic_vector(7 downto 0); SIGNAL rxprbssel_in : std_logic_vector(31 downto 0); SIGNAL rxprogdivreset_in : std_logic_vector(7 downto 0); SIGNAL rxrate_in : std_logic_vector(23 downto 0); SIGNAL rxslide_in : std_logic_vector(7 downto 0); SIGNAL rxtermination_in : std_logic_vector(7 downto 0); SIGNAL rxuserrdy_in : std_logic_vector(7 downto 0); SIGNAL rxusrclk2_in : std_logic_vector(7 downto 0); SIGNAL rxusrclk_in : std_logic_vector(7 downto 0); SIGNAL tx8b10ben_in : std_logic_vector(7 downto 0); SIGNAL txctrl0_in : std_logic_vector(127 downto 0); SIGNAL txctrl1_in : std_logic_vector(127 downto 0); SIGNAL txctrl2_in : std_logic_vector(63 downto 0); SIGNAL txdata_in : std_logic_vector(1023 downto 0); SIGNAL txdeemph_in : std_logic_vector(15 downto 0); SIGNAL txdetectrx_in : std_logic_vector(7 downto 0); SIGNAL txdiffctrl_in : std_logic_vector(39 downto 0); SIGNAL txdlybypass_in : std_logic_vector(7 downto 0); SIGNAL txdlyen_in : std_logic_vector(7 downto 0); SIGNAL txdlyhold_in : std_logic_vector(7 downto 0); SIGNAL txdlyovrden_in : std_logic_vector(7 downto 0); SIGNAL txdlysreset_in : std_logic_vector(7 downto 0); SIGNAL txdlyupdown_in : std_logic_vector(7 downto 0); SIGNAL txelecidle_in : std_logic_vector(7 downto 0); SIGNAL txmaincursor_in : std_logic_vector(55 downto 0); SIGNAL txmargin_in : std_logic_vector(23 downto 0); SIGNAL txoutclksel_in : std_logic_vector(23 downto 0); SIGNAL txpcsreset_in : std_logic_vector(7 downto 0); SIGNAL txpd_in : std_logic_vector(15 downto 0); SIGNAL txphalign_in : std_logic_vector(7 downto 0); SIGNAL txphalignen_in : std_logic_vector(7 downto 0); SIGNAL txphdlypd_in : std_logic_vector(7 downto 0); SIGNAL txphdlyreset_in : std_logic_vector(7 downto 0); SIGNAL txphdlytstclk_in : std_logic_vector(7 downto 0); SIGNAL txphinit_in : std_logic_vector(7 downto 0); SIGNAL txphovrden_in : std_logic_vector(7 downto 0); SIGNAL rxratemode_in : std_logic_vector(7 downto 0); SIGNAL txpmareset_in : std_logic_vector(7 downto 0); SIGNAL txpostcursor_in : std_logic_vector(39 downto 0); SIGNAL txprbsforceerr_in : std_logic_vector(7 downto 0); SIGNAL txprbssel_in : std_logic_vector(31 downto 0); SIGNAL txprecursor_in : std_logic_vector(39 downto 0); SIGNAL txprogdivreset_in : std_logic_vector(7 downto 0); SIGNAL txrate_in : std_logic_vector(23 downto 0); SIGNAL txswing_in : std_logic_vector(7 downto 0); SIGNAL txsyncallin_in : std_logic_vector(7 downto 0); SIGNAL txsyncin_in : std_logic_vector(7 downto 0); SIGNAL txsyncmode_in : std_logic_vector(7 downto 0); SIGNAL txuserrdy_in : std_logic_vector(7 downto 0); SIGNAL txusrclk2_in : std_logic_vector(7 downto 0); SIGNAL txusrclk_in : std_logic_vector(7 downto 0); SIGNAL drpclk_in : std_logic; SIGNAL drpaddr_in : std_logic_vector(79 downto 0); SIGNAL drpen_in : std_logic_vector(7 downto 0); SIGNAL drprst_in : std_logic_vector(7 downto 0); SIGNAL drpwe_in : std_logic_vector(7 downto 0); SIGNAL drpdi_in : std_logic_vector(127 downto 0); SIGNAL ext_phy_clk_bufg_gt_ce : std_logic; SIGNAL ext_phy_clk_bufg_gt_reset : std_logic; SIGNAL ext_phy_clk_rst_idle : std_logic; SIGNAL ext_phy_clk_txoutclk : std_logic; SIGNAL ext_phy_clk_bufgtcemask : std_logic; SIGNAL ext_phy_clk_gt_bufgtrstmask : std_logic; SIGNAL ext_phy_clk_bufgtdiv : std_logic_vector(8 downto 0); SIGNAL phy_rdy_out : std_logic; SIGNAL sys_reset : std_logic; SIGNAL in_packet_reg : std_logic; SIGNAL cfg_bus_number_sub : std_logic_vector(7 downto 0); SIGNAL cfg_dsn_sub : std_logic_vector(63 downto 0); SIGNAL cfg_flr_done_sub : std_logic_vector(3 downto 0); SIGNAL cfg_vf_flr_done_sub : std_logic_vector(0 downto 0); SIGNAL sys_clk_sub : std_logic; CONSTANT PL_LINK_CAP_MAX_LINK_WIDTH : integer := 1; -- 1- X1; 2 - X2; 4 - X4; 8 - X8; 16 - X16 CONSTANT C_DATA_WIDTH : integer := 64; -- RX/TX interface data width CONSTANT AXISTEN_IF_MC_RX_STRADDLE : integer := 0; CONSTANT PL_LINK_CAP_MAX_LINK_SPEED : integer := 2; -- 1- GEN1; 2 - GEN2; 4 - GEN3; 8 - GEN4 CONSTANT KEEP_WIDTH : integer := C_DATA_WIDTH / 32; CONSTANT EXT_PIPE_SIM : BOOLEAN := FALSE; -- This CONSTANT has effect on selecting Enable External PIPE Interface in GUI. CONSTANT AXISTEN_IF_CC_ALIGNMENT_MODE : BOOLEAN := FALSE; CONSTANT AXISTEN_IF_CQ_ALIGNMENT_MODE : BOOLEAN := FALSE; CONSTANT AXISTEN_IF_RQ_ALIGNMENT_MODE : BOOLEAN := FALSE; CONSTANT AXISTEN_IF_RC_ALIGNMENT_MODE : BOOLEAN := FALSE; CONSTANT AXI4_CQ_TUSER_WIDTH : integer := 88; CONSTANT AXI4_CC_TUSER_WIDTH : integer := 33; CONSTANT AXI4_RQ_TUSER_WIDTH : integer := 62; CONSTANT AXI4_RC_TUSER_WIDTH : integer := 75; CONSTANT AXISTEN_IF_ENABLE_CLIENT_TAG : integer := 0; CONSTANT RQ_AVAIL_TAG_IDX : integer := 8; CONSTANT RQ_AVAIL_TAG : integer := 256; CONSTANT AXISTEN_IF_RQ_PARITY_CHECK : integer := 0; CONSTANT AXISTEN_IF_CC_PARITY_CHECK : integer := 0; CONSTANT AXISTEN_IF_RC_PARITY_CHECK : integer := 0; CONSTANT AXISTEN_IF_CQ_PARITY_CHECK : integer := 0; CONSTANT AXISTEN_IF_ENABLE_RX_MSG_INTFC : BOOLEAN := FALSE; --CONSTANT AXISTEN_IF_ENABLE_MSG_ROUTE : std_logic_vector(17 downto 0) := X"2FFFF"; --------- COMPONENT DECLARATIONS (introducing the IPs) -------------------------- COMPONENT pcie4_uscale_plus_0 PORT ( pci_exp_txn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); pci_exp_txp : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); pci_exp_rxn : IN STD_LOGIC_VECTOR(0 DOWNTO 0); pci_exp_rxp : IN STD_LOGIC_VECTOR(0 DOWNTO 0); user_clk : OUT STD_LOGIC; user_reset : OUT STD_LOGIC; user_lnk_up : OUT STD_LOGIC; s_axis_rq_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_rq_tkeep : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axis_rq_tlast : IN STD_LOGIC; s_axis_rq_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axis_rq_tuser : IN STD_LOGIC_VECTOR(61 DOWNTO 0); s_axis_rq_tvalid : IN STD_LOGIC; m_axis_rc_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_rc_tkeep : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axis_rc_tlast : OUT STD_LOGIC; m_axis_rc_tready : IN STD_LOGIC; m_axis_rc_tuser : OUT STD_LOGIC_VECTOR(74 DOWNTO 0); m_axis_rc_tvalid : OUT STD_LOGIC; m_axis_cq_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_cq_tkeep : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axis_cq_tlast : OUT STD_LOGIC; m_axis_cq_tready : IN STD_LOGIC; m_axis_cq_tuser : OUT STD_LOGIC_VECTOR(87 DOWNTO 0); m_axis_cq_tvalid : OUT STD_LOGIC; s_axis_cc_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_cc_tkeep : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axis_cc_tlast : IN STD_LOGIC; s_axis_cc_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axis_cc_tuser : IN STD_LOGIC_VECTOR(32 DOWNTO 0); s_axis_cc_tvalid : IN STD_LOGIC; pcie_rq_seq_num0 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); pcie_rq_seq_num_vld0 : OUT STD_LOGIC; pcie_rq_seq_num1 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); pcie_rq_seq_num_vld1 : OUT STD_LOGIC; pcie_rq_tag0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); pcie_rq_tag1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); pcie_rq_tag_av : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); pcie_rq_tag_vld0 : OUT STD_LOGIC; pcie_rq_tag_vld1 : OUT STD_LOGIC; pcie_tfc_nph_av : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); pcie_tfc_npd_av : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); pcie_cq_np_req : IN STD_LOGIC_VECTOR(1 DOWNTO 0); pcie_cq_np_req_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); cfg_phy_link_down : OUT STD_LOGIC; cfg_phy_link_status : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); cfg_negotiated_width : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); cfg_current_speed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); cfg_max_payload : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); cfg_max_read_req : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); cfg_function_status : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); cfg_function_power_state : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); cfg_vf_status : OUT STD_LOGIC_VECTOR(503 DOWNTO 0); cfg_vf_power_state : OUT STD_LOGIC_VECTOR(755 DOWNTO 0); cfg_link_power_state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); cfg_mgmt_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); cfg_mgmt_function_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0); cfg_mgmt_write : IN STD_LOGIC; cfg_mgmt_write_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); cfg_mgmt_byte_enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); cfg_mgmt_read : IN STD_LOGIC; cfg_mgmt_read_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); cfg_mgmt_read_write_done : OUT STD_LOGIC; cfg_mgmt_debug_access : IN STD_LOGIC; cfg_err_cor_out : OUT STD_LOGIC; cfg_err_nonfatal_out : OUT STD_LOGIC; cfg_err_fatal_out : OUT STD_LOGIC; cfg_local_error_valid : OUT STD_LOGIC; cfg_local_error_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); cfg_ltssm_state : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); cfg_rx_pm_state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); cfg_tx_pm_state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); cfg_rcb_status : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cfg_obff_enable : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); cfg_pl_status_change : OUT STD_LOGIC; cfg_tph_requester_enable : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cfg_tph_st_mode : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); cfg_vf_tph_requester_enable : OUT STD_LOGIC_VECTOR(251 DOWNTO 0); cfg_vf_tph_st_mode : OUT STD_LOGIC_VECTOR(755 DOWNTO 0); cfg_msg_received : OUT STD_LOGIC; cfg_msg_received_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); cfg_msg_received_type : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); cfg_msg_transmit : IN STD_LOGIC; cfg_msg_transmit_type : IN STD_LOGIC_VECTOR(2 DOWNTO 0); cfg_msg_transmit_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); cfg_msg_transmit_done : OUT STD_LOGIC; cfg_fc_ph : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); cfg_fc_pd : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); cfg_fc_nph : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); cfg_fc_npd : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); cfg_fc_cplh : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); cfg_fc_cpld : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); cfg_fc_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); cfg_dsn : IN STD_LOGIC_VECTOR(63 DOWNTO 0); cfg_bus_number : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); cfg_power_state_change_ack : IN STD_LOGIC; cfg_power_state_change_interrupt : OUT STD_LOGIC; cfg_err_cor_in : IN STD_LOGIC; cfg_err_uncor_in : IN STD_LOGIC; cfg_flr_in_process : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cfg_flr_done : IN STD_LOGIC_VECTOR(3 DOWNTO 0); cfg_vf_flr_in_process : OUT STD_LOGIC_VECTOR(251 DOWNTO 0); cfg_vf_flr_func_num : IN STD_LOGIC_VECTOR(7 DOWNTO 0); cfg_vf_flr_done : IN STD_LOGIC_VECTOR(0 DOWNTO 0); cfg_link_training_enable : IN STD_LOGIC; cfg_interrupt_int : IN STD_LOGIC_VECTOR(3 DOWNTO 0); cfg_interrupt_pending : IN STD_LOGIC_VECTOR(3 DOWNTO 0); cfg_interrupt_sent : OUT STD_LOGIC; cfg_interrupt_msi_enable : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cfg_interrupt_msi_mmenable : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); cfg_interrupt_msi_mask_update : OUT STD_LOGIC; cfg_interrupt_msi_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); cfg_interrupt_msi_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0); cfg_interrupt_msi_int : IN STD_LOGIC_VECTOR(31 DOWNTO 0); cfg_interrupt_msi_pending_status : IN STD_LOGIC_VECTOR(31 DOWNTO 0); cfg_interrupt_msi_pending_status_data_enable : IN STD_LOGIC; cfg_interrupt_msi_pending_status_function_num : IN STD_LOGIC_VECTOR(1 DOWNTO 0); cfg_interrupt_msi_sent : OUT STD_LOGIC; cfg_interrupt_msi_fail : OUT STD_LOGIC; cfg_interrupt_msi_attr : IN STD_LOGIC_VECTOR(2 DOWNTO 0); cfg_interrupt_msi_tph_present : IN STD_LOGIC; cfg_interrupt_msi_tph_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); cfg_interrupt_msi_tph_st_tag : IN STD_LOGIC_VECTOR(7 DOWNTO 0); cfg_interrupt_msi_function_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0); cfg_pm_aspm_l1_entry_reject : IN STD_LOGIC; cfg_pm_aspm_tx_l0s_entry_disable : IN STD_LOGIC; cfg_hot_reset_out : OUT STD_LOGIC; cfg_config_space_enable : IN STD_LOGIC; cfg_req_pm_transition_l23_ready : IN STD_LOGIC; cfg_hot_reset_in : IN STD_LOGIC; cfg_ds_port_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0); cfg_ds_bus_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0); cfg_ds_device_number : IN STD_LOGIC_VECTOR(4 DOWNTO 0); sys_clk : IN STD_LOGIC; sys_clk_gt : IN STD_LOGIC; sys_reset : IN STD_LOGIC; gt_pcieuserratedone : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gt_loopback : IN STD_LOGIC_VECTOR(2 DOWNTO 0); gt_txprbsforceerr : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txinhibit : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txprbssel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); gt_rxprbssel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); gt_rxprbscntreset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txelecidle : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxpmaresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txphaligndone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txphinitdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txdlysresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxphaligndone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxdlysresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxsyncdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_eyescandataerror : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxprbserr : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_dmonfiforeset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gt_dmonitorclk : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gt_dmonitorout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); gt_rxcommadet : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_phystatus : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxvalid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxcdrlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_pcierateidle : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_pcieuserratestart : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_gtpowergood : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_cplllock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxoutclk : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxrecclkout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_qpll1lock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_qpll0lock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); gt_rxbufstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); gt_bufgtdiv : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); phy_txeq_ctrl : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); phy_txeq_preset : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); phy_rst_fsm : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); phy_txeq_fsm : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); phy_rxeq_fsm : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); phy_rst_idle : OUT STD_LOGIC; phy_rrst_n : OUT STD_LOGIC; phy_prst_n : OUT STD_LOGIC; gt_gen34_eios_det : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txoutclk : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txoutclkfabric : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxoutclkfabric : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txoutclkpcs : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxoutclkpcs : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txpmareset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxpmareset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txpcsreset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxpcsreset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxbufreset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxcdrreset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxdfelpmreset : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txprogdivresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txpmaresetdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_txsyncdone : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gt_rxprbslocked : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); phy_rdy_out : OUT STD_LOGIC ); END COMPONENT; --architecture body start ------------------------------------------------------- begin --------- COMPONENT INSTALLATIONS (connecting the IPs to local signals) --------- xilinx_pcie_ip : pcie4_uscale_plus_0 PORT MAP ( pci_exp_txn(0) => pci_exp_txn, pci_exp_txp(0) => pci_exp_txp, pci_exp_rxn(0) => pci_exp_rxn, pci_exp_rxp(0) => pci_exp_rxp, user_clk => user_clk , user_reset => user_reset , user_lnk_up => user_lnk_up , phy_rdy_out => phy_rdy_out , s_axis_rq_tlast => s_axis_rq_tlast , s_axis_rq_tdata => s_axis_rq_tdata , s_axis_rq_tuser => s_axis_rq_tuser , s_axis_rq_tkeep => s_axis_rq_tkeep , s_axis_rq_tready => s_axis_rq_tready , s_axis_rq_tvalid => s_axis_rq_tvalid , m_axis_rc_tdata => m_axis_rc_tdata , m_axis_rc_tuser => m_axis_rc_tuser , m_axis_rc_tlast => m_axis_rc_tlast , m_axis_rc_tkeep => m_axis_rc_tkeep , m_axis_rc_tvalid => m_axis_rc_tvalid , m_axis_rc_tready => m_axis_rc_tready , m_axis_cq_tdata => m_axis_cq_tdata , m_axis_cq_tuser => m_axis_cq_tuser , m_axis_cq_tlast => m_axis_cq_tlast , m_axis_cq_tkeep => m_axis_cq_tkeep , m_axis_cq_tvalid => m_axis_cq_tvalid , m_axis_cq_tready => m_axis_cq_tready , s_axis_cc_tdata => s_axis_cc_tdata , s_axis_cc_tuser => s_axis_cc_tuser , s_axis_cc_tlast => s_axis_cc_tlast , s_axis_cc_tkeep => s_axis_cc_tkeep , s_axis_cc_tvalid => s_axis_cc_tvalid , s_axis_cc_tready => s_axis_cc_tready , gt_pcieuserratedone => (OTHERS => '0'), gt_loopback => (OTHERS => '0'), gt_txprbsforceerr => (OTHERS => '0'), gt_txinhibit => (OTHERS => '0'), gt_txprbssel => (OTHERS => '0'), gt_rxprbssel => (OTHERS => '0'), gt_rxprbscntreset => (OTHERS => '0'), -- gt_rxcdrlock => , -- gt_pcierateidle => , -- gt_pcieuserratestart => , -- gt_gtpowergood => , -- gt_rxoutclk => , -- gt_rxrecclkout => , -- gt_txresetdone => , -- gt_rxpmaresetdone => , -- gt_rxresetdone => , -- gt_rxbufstatus => , -- gt_txphaligndone => , -- gt_txphinitdone => , -- gt_txdlysresetdone => , -- gt_rxphaligndone => , -- gt_rxdlysresetdone => , -- gt_rxsyncdone => , -- gt_cplllock => , -- gt_qpll0lock => , -- gt_qpll1lock => , -- gt_eyescandataerror => , -- gt_rxprbserr => , -- gt_dmonitorout => , gt_dmonfiforeset => (OTHERS => '0'), gt_dmonitorclk => (OTHERS => '0'), -- gt_rxcommadet => , -- gt_txelecidle => , -- gt_rxvalid => , -- gt_bufgtdiv => , -- phy_rrst_n => , -- phy_txeq_ctrl => , -- phy_txeq_preset => , -- phy_txeq_fsm => , -- phy_rxeq_fsm => , -- phy_rst_idle => , -- gt_gen34_eios_det => , -- gt_txoutclk => , -- gt_txoutclkfabric => , -- gt_rxoutclkfabric => , -- gt_txoutclkpcs => , -- gt_rxoutclkpcs => , gt_txpmareset => (OTHERS => '0'), gt_rxpmareset => (OTHERS => '0'), gt_txpcsreset => (OTHERS => '0'), gt_rxpcsreset => (OTHERS => '0'), gt_rxbufreset => (OTHERS => '0'), gt_rxcdrreset => (OTHERS => '0'), gt_rxdfelpmreset => (OTHERS => '0'), -- gt_txprogdivresetdone => , -- gt_txpmaresetdone => , -- gt_txsyncdone => , -- gt_rxprbslocked => , -- phy_prst_n => , -- phy_rst_fsm => , -- gt_phystatus => , -- gt_rxstatus => , pcie_tfc_nph_av => pcie_tfc_nph_av , pcie_tfc_npd_av => pcie_tfc_npd_av , pcie_rq_seq_num0 => pcie_rq_seq_num0 , pcie_rq_seq_num_vld0 => pcie_rq_seq_num_vld0 , pcie_rq_seq_num1 => pcie_rq_seq_num1 , pcie_rq_seq_num_vld1 => pcie_rq_seq_num_vld1 , -- pcie_rq_tag0 => , -- pcie_rq_tag1 => , -- pcie_rq_tag_av => , -- pcie_rq_tag_vld0 => , -- pcie_rq_tag_vld1 => , pcie_cq_np_req => pcie_cq_np_req , pcie_cq_np_req_count => pcie_cq_np_req_count , cfg_phy_link_down => cfg_phy_link_down , -- cfg_phy_link_status => , cfg_negotiated_width => cfg_negotiated_width , cfg_current_speed => cfg_current_speed , cfg_max_payload => cfg_max_payload , cfg_max_read_req => cfg_max_read_req , cfg_function_status => cfg_function_status , cfg_function_power_state => cfg_function_power_state , cfg_vf_status => cfg_vf_status , -- cfg_vf_power_state => , cfg_link_power_state => cfg_link_power_state , cfg_err_cor_out => cfg_err_cor_out , cfg_err_nonfatal_out => cfg_err_nonfatal_out , cfg_err_fatal_out => cfg_err_fatal_out , -- cfg_local_error_out => , -- cfg_local_error_valid => , cfg_ltssm_state => cfg_ltssm_state , -- cfg_rx_pm_state => , -- cfg_tx_pm_state => , cfg_rcb_status => cfg_rcb_status , cfg_obff_enable => cfg_obff_enable , cfg_pl_status_change => cfg_pl_status_change , -- cfg_tph_requester_enable => , -- cfg_tph_st_mode => , -- cfg_vf_tph_requester_enable => , -- cfg_vf_tph_st_mode => , cfg_mgmt_addr => cfg_mgmt_addr , cfg_mgmt_write => cfg_mgmt_write , cfg_mgmt_write_data => cfg_mgmt_write_data , cfg_mgmt_byte_enable => cfg_mgmt_byte_enable , cfg_mgmt_read => cfg_mgmt_read , cfg_mgmt_read_data => cfg_mgmt_read_data , cfg_mgmt_read_write_done => cfg_mgmt_read_write_done , cfg_mgmt_debug_access => '0', cfg_mgmt_function_number => (OTHERS => '0'), cfg_pm_aspm_l1_entry_reject => '0', cfg_pm_aspm_tx_l0s_entry_disable => '1', cfg_msg_received => cfg_msg_received , cfg_msg_received_data => cfg_msg_received_data , cfg_msg_received_type => cfg_msg_received_type , cfg_msg_transmit => cfg_msg_transmit , cfg_msg_transmit_type => cfg_msg_transmit_type , cfg_msg_transmit_data => cfg_msg_transmit_data , cfg_msg_transmit_done => cfg_msg_transmit_done , cfg_fc_ph => cfg_fc_ph , cfg_fc_pd => cfg_fc_pd , cfg_fc_nph => cfg_fc_nph , cfg_fc_npd => cfg_fc_npd , cfg_fc_cplh => cfg_fc_cplh , cfg_fc_cpld => cfg_fc_cpld , cfg_fc_sel => cfg_fc_sel , cfg_bus_number => cfg_bus_number_sub, cfg_dsn => cfg_dsn_sub , cfg_power_state_change_ack => cfg_power_state_change_ack , cfg_power_state_change_interrupt => cfg_power_state_change_interrupt , cfg_err_cor_in => cfg_err_cor_in , cfg_err_uncor_in => cfg_err_uncor_in , cfg_flr_in_process => cfg_flr_in_process , cfg_flr_done => cfg_flr_done_sub , cfg_vf_flr_in_process => cfg_vf_flr_in_process , cfg_vf_flr_done => cfg_vf_flr_done_sub , cfg_link_training_enable => cfg_link_training_enable , cfg_hot_reset_out => cfg_hot_reset_out , cfg_config_space_enable => cfg_config_space_enable , cfg_req_pm_transition_l23_ready => cfg_req_pm_transition_l23_ready , cfg_hot_reset_in => cfg_hot_reset_in , cfg_ds_bus_number => cfg_ds_bus_number , cfg_ds_device_number => cfg_ds_device_number , cfg_ds_port_number => cfg_ds_port_number , cfg_vf_flr_func_num => cfg_vf_flr_func_num, cfg_interrupt_int => cfg_interrupt_int , cfg_interrupt_pending => cfg_interrupt_pending , cfg_interrupt_sent => cfg_interrupt_sent , cfg_interrupt_msi_enable => cfg_interrupt_msi_enable , cfg_interrupt_msi_mmenable => cfg_interrupt_msi_mmenable , cfg_interrupt_msi_mask_update => cfg_interrupt_msi_mask_update , cfg_interrupt_msi_data => cfg_interrupt_msi_data , cfg_interrupt_msi_select => cfg_interrupt_msi_select , cfg_interrupt_msi_int => cfg_interrupt_msi_int , cfg_interrupt_msi_pending_status => cfg_interrupt_msi_pending_status (31 downto 0), cfg_interrupt_msi_sent => cfg_interrupt_msi_sent , cfg_interrupt_msi_fail => cfg_interrupt_msi_fail , cfg_interrupt_msi_attr => cfg_interrupt_msi_attr , cfg_interrupt_msi_tph_present => cfg_interrupt_msi_tph_present , cfg_interrupt_msi_tph_type => cfg_interrupt_msi_tph_type , cfg_interrupt_msi_tph_st_tag => cfg_interrupt_msi_tph_st_tag , cfg_interrupt_msi_pending_status_function_num => "00", cfg_interrupt_msi_pending_status_data_enable => '0', cfg_interrupt_msi_function_number => cfg_interrupt_msi_function_number , sys_clk => sys_clk_sub , sys_clk_gt => sys_clk_gt , sys_reset => sys_reset ); -- local Logic ------------------------------------------------------------------ sys_reset <= not sys_reset_n; --AXI4S-TRN conversions: --start of frame, remainder-keep logic, data path DWORD-endian-reordering --general rule: TRN_T* to S_AXIS_CC*, while TRN_R* to M_AXIS_CQ*, TRN_FC* to CFG_FC*. -- SIGNALS TO THIS FILE TOP OUTPUTS. trn_lnk_up_n <= not user_lnk_up ; -- Tx trn_tdst_rdy_n <= not s_axis_cc_tready(0) ; trn_terr_drop_n <= '1'; trn_tbuf_av <= "000000"; trn_tcfg_req_n <= '1'; -- Rx trn_rd(63 downto 32) <= m_axis_cq_tdata(31 downto 0); --endian swap trn_rd(31 downto 0) <= m_axis_cq_tdata(63 downto 32); trn_rsof_n <= not (m_axis_cq_tvalid and (not in_packet_reg)); process ( sys_reset_n, user_clk) begin if (sys_reset_n = '0') then in_packet_reg <='0'; elsif (user_clk'event and user_clk = '1') then if (m_axis_cq_tvalid='1' and m_axis_cq_tready='1') then in_packet_reg <= not m_axis_cq_tlast; end if; end if; end process; trn_reof_n <= not m_axis_cq_tlast ; trn_rsrc_rdy_n <= not m_axis_cq_tvalid; trn_rsrc_dsc_n <= '0'; trn_rerrfwd_n <= not m_axis_cq_tuser(1); trn_rbar_hit_n <= not m_axis_cq_tuser(8 downto 2); trn_fc_nph <= cfg_fc_nph ; trn_fc_npd <= cfg_fc_npd ; trn_fc_ph <= cfg_fc_ph ; trn_fc_pd <= cfg_fc_pd ; trn_fc_cplh <= cfg_fc_cplh; trn_fc_cpld <= cfg_fc_cpld; -- Host (CFG) Interface cfg_do <= (OTHERS => '0'); cfg_rd_wr_done_n <= not cfg_mgmt_read_write_done; cfg_err_cpl_rdy_n <= '1'; cfg_interrupt_rdy_n <= '1'; cfg_interrupt_do <= (OTHERS => '0'); cfg_interrupt_mmenable <= (OTHERS => '0'); cfg_interrupt_msienable <= cfg_interrupt_msi_enable(0); cfg_to_turnoff_n <= '1'; cfg_pcie_link_state_n(1 downto 0) <= cfg_phy_link_status; cfg_pcie_link_state_n(2) <= cfg_phy_link_down; cfg_bus_number <= cfg_bus_number_sub; cfg_device_number <= (OTHERS => '0'); --the new core doesnt provide this, so we assume 0. On PCI-express, each device is on a different bus, and device number=0. this core is simple, so func.num=0 too. cfg_function_number <= (OTHERS => '0'); cfg_status <= (OTHERS => '0'); cfg_command <= (OTHERS => '0'); cfg_dstatus <= (OTHERS => '0'); cfg_dcommand <= (OTHERS => '0'); cfg_lstatus <= (OTHERS => '0'); cfg_lcommand <= (OTHERS => '0'); -- System Interface trn_clk <= user_clk; trn_reset_n <= not user_reset; received_hot_reset <= cfg_hot_reset_out; --IP BELOW INPUTS: s_axis_rq_tdata <= (OTHERS => '0'); s_axis_rq_tkeep <= (OTHERS => '0'); s_axis_rq_tlast <= '0'; s_axis_rq_tuser <= (OTHERS => '0'); s_axis_rq_tvalid <= '0'; m_axis_rc_tready <= '0'; m_axis_cq_tready <= not trn_rdst_rdy_n; --CQ=RX s_axis_cc_tdata(63 downto 32) <= trn_td(31 downto 0); --endian swap. CC=TX s_axis_cc_tdata(31 downto 0) <= trn_td(63 downto 32); --since the trn_term signal is missing on TRN, I try to re-creste it here: --s_axis_cc_tkeep <= "11"; --try to force this to all dwords always valid = "11" --s_axis_cc_tkeep <= "01"; --try to force this to 32bit valid = "01" or "10" ??? --it would be correct like this, but trn_term is missing, xilinx suggestion: --process ( sys_reset_n, user_clk) --begin --if (sys_reset_n = '0') then --s_axis_cc_tkeep <=(OTHERS => '0'); --elsif (user_clk'event and user_clk = '1') then --if (s_axis_cc_tlast ='1') then --if (trn_trem_n='1') then --missing signal on TRN interface. signal last dword of burst --s_axis_cc_tkeep <= "01"; --else --s_axis_cc_tkeep <= "11"; --end if; --else --s_axis_cc_tkeep <= "11"; --end if; --end if; --end process; --or try another trick, using end of frame: (async, so slow timing, but should work at 62MHz) process ( sys_reset_n, user_clk, s_axis_cc_tlast, trn_teof_n) begin if (sys_reset_n = '0') then s_axis_cc_tkeep <=(OTHERS => '0'); else --elsif (user_clk'event and user_clk = '1') then if (s_axis_cc_tlast ='1') then if (trn_teof_n='0') then s_axis_cc_tkeep <= "01"; else s_axis_cc_tkeep <= "11"; end if; else s_axis_cc_tkeep <= "11"; end if; end if; end process; s_axis_cc_tlast <= not trn_teof_n; s_axis_cc_tuser(3) <= not trn_tsrc_dsc_n; s_axis_cc_tuser(2) <= not trn_tstr_n; s_axis_cc_tuser(1) <= not trn_terrfwd_n; s_axis_cc_tuser(0) <= '0'; s_axis_cc_tvalid <= not trn_tsrc_rdy_n; pcie_cq_np_req <= "00"; cfg_mgmt_addr <= (OTHERS => '0'); cfg_mgmt_function_number <= (OTHERS => '0'); cfg_mgmt_write <= '0'; cfg_mgmt_write_data <= (OTHERS => '0'); cfg_mgmt_byte_enable <= (OTHERS => '0'); cfg_mgmt_read <= '0'; cfg_mgmt_debug_access <= '0'; cfg_msg_transmit <= '0'; cfg_msg_transmit_type <= (OTHERS => '0'); cfg_msg_transmit_data <= (OTHERS => '0'); cfg_fc_sel <= trn_fc_sel; cfg_dsn_sub <= (OTHERS => '0'); --or cfg_dsn; cfg_power_state_change_ack <= '0'; cfg_err_cor_in <= '0'; cfg_err_uncor_in <= '0'; cfg_flr_done_sub <= (OTHERS => '0'); --or cfg_flr_done; cfg_vf_flr_func_num <= (OTHERS => '0'); cfg_vf_flr_done_sub <= (OTHERS => '0'); --or cfg_vf_flr_done; cfg_link_training_enable <= '1'; cfg_interrupt_int <= (OTHERS => '0'); cfg_interrupt_pending <= (OTHERS => '0'); cfg_interrupt_msi_select <= (OTHERS => '0'); cfg_interrupt_msi_int <= (OTHERS => '0'); cfg_interrupt_msi_pending_status <= (OTHERS => '0'); cfg_interrupt_msi_pending_status_data_enable <= '0'; cfg_interrupt_msi_pending_status_function_num <= (OTHERS => '0'); cfg_interrupt_msi_attr <= (OTHERS => '0'); cfg_interrupt_msi_tph_present <= '0'; cfg_interrupt_msi_tph_type <= (OTHERS => '0'); cfg_interrupt_msi_tph_st_tag <= (OTHERS => '0'); cfg_interrupt_msi_function_number <= (OTHERS => '0'); cfg_pm_aspm_l1_entry_reject <= '0'; cfg_pm_aspm_tx_l0s_entry_disable <= '0'; cfg_config_space_enable <= '1'; cfg_req_pm_transition_l23_ready <= '0'; cfg_hot_reset_in <= '0'; cfg_ds_port_number <= (OTHERS => '0'); cfg_ds_bus_number <= (OTHERS => '0'); cfg_ds_device_number <= (OTHERS => '0'); sys_clk_sub <= sys_clk; --the 100/125/250M reference clock sys_clk_gt <= sys_clk2; sys_reset <= not sys_reset_n; gt_pcieuserratedone <= (OTHERS => '0'); gt_loopback <= (OTHERS => '0'); gt_txprbsforceerr <= (OTHERS => '0'); gt_txinhibit <= (OTHERS => '0'); gt_txprbssel <= (OTHERS => '0'); gt_rxprbssel <= (OTHERS => '0'); gt_rxprbscntreset <= (OTHERS => '0'); gt_dmonfiforeset <= (OTHERS => '0'); gt_dmonitorclk <= (OTHERS => '0'); gt_txpmareset <= (OTHERS => '0'); gt_rxpmareset <= (OTHERS => '0'); gt_txpcsreset <= (OTHERS => '0'); gt_rxpcsreset <= (OTHERS => '0'); gt_rxbufreset <= (OTHERS => '0'); gt_rxcdrreset <= (OTHERS => '0'); gt_rxdfelpmreset <= (OTHERS => '0'); --end file ---------------------------------------------------------------------- end rtl;