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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [sysgen/] [nonleaf_results.vhd] - Rev 13
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library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "INOUT_LOGIC" entity inout_logic is port ( data_out: in std_logic; data_out_x0: in std_logic_vector(31 downto 0); data_out_x1: in std_logic_vector(31 downto 0); data_out_x10: in std_logic; data_out_x11: in std_logic; data_out_x12: in std_logic_vector(31 downto 0); data_out_x13: in std_logic; data_out_x14: in std_logic_vector(31 downto 0); data_out_x15: in std_logic; data_out_x16: in std_logic_vector(31 downto 0); data_out_x17: in std_logic; data_out_x18: in std_logic_vector(31 downto 0); data_out_x19: in std_logic; data_out_x2: in std_logic; data_out_x20: in std_logic_vector(31 downto 0); data_out_x21: in std_logic; data_out_x22: in std_logic_vector(31 downto 0); data_out_x23: in std_logic; data_out_x24: in std_logic_vector(31 downto 0); data_out_x25: in std_logic_vector(31 downto 0); data_out_x26: in std_logic; data_out_x3: in std_logic_vector(31 downto 0); data_out_x4: in std_logic; data_out_x5: in std_logic_vector(31 downto 0); data_out_x6: in std_logic; data_out_x7: in std_logic_vector(31 downto 0); data_out_x8: in std_logic; data_out_x9: in std_logic_vector(31 downto 0); debug_in_1i: in std_logic_vector(31 downto 0); debug_in_2i: in std_logic_vector(31 downto 0); debug_in_3i: in std_logic_vector(31 downto 0); debug_in_4i: in std_logic_vector(31 downto 0); dma_host2board_busy: in std_logic; dma_host2board_done: in std_logic; reg01_td: in std_logic_vector(31 downto 0); reg01_tv: in std_logic; reg02_td: in std_logic_vector(31 downto 0); reg02_tv: in std_logic; reg03_td: in std_logic_vector(31 downto 0); reg03_tv: in std_logic; reg04_td: in std_logic_vector(31 downto 0); reg04_tv: in std_logic; reg05_td: in std_logic_vector(31 downto 0); reg05_tv: in std_logic; reg06_td: in std_logic_vector(31 downto 0); reg06_tv: in std_logic; reg07_td: in std_logic_vector(31 downto 0); reg07_tv: in std_logic; reg08_td: in std_logic_vector(31 downto 0); reg08_tv: in std_logic; reg09_td: in std_logic_vector(31 downto 0); reg09_tv: in std_logic; reg10_td: in std_logic_vector(31 downto 0); reg10_tv: in std_logic; reg11_td: in std_logic_vector(31 downto 0); reg11_tv: in std_logic; reg12_td: in std_logic_vector(31 downto 0); reg12_tv: in std_logic; reg13_td: in std_logic_vector(31 downto 0); reg13_tv: in std_logic; reg14_td: in std_logic_vector(31 downto 0); reg14_tv: in std_logic; data_in: out std_logic_vector(31 downto 0); data_in_x0: out std_logic; data_in_x1: out std_logic_vector(31 downto 0); data_in_x10: out std_logic_vector(31 downto 0); data_in_x11: out std_logic_vector(31 downto 0); data_in_x12: out std_logic; data_in_x13: out std_logic_vector(31 downto 0); data_in_x14: out std_logic; data_in_x15: out std_logic_vector(31 downto 0); data_in_x16: out std_logic; data_in_x17: out std_logic_vector(31 downto 0); data_in_x18: out std_logic; data_in_x19: out std_logic_vector(31 downto 0); data_in_x2: out std_logic; data_in_x20: out std_logic; data_in_x21: out std_logic; data_in_x22: out std_logic_vector(31 downto 0); data_in_x23: out std_logic; data_in_x24: out std_logic_vector(31 downto 0); data_in_x25: out std_logic; data_in_x26: out std_logic_vector(31 downto 0); data_in_x27: out std_logic; data_in_x28: out std_logic_vector(31 downto 0); data_in_x29: out std_logic_vector(31 downto 0); data_in_x3: out std_logic_vector(31 downto 0); data_in_x30: out std_logic_vector(31 downto 0); data_in_x31: out std_logic; data_in_x32: out std_logic_vector(31 downto 0); data_in_x4: out std_logic; data_in_x5: out std_logic_vector(31 downto 0); data_in_x6: out std_logic; data_in_x7: out std_logic_vector(31 downto 0); data_in_x8: out std_logic; data_in_x9: out std_logic; en: out std_logic; en_x0: out std_logic; en_x1: out std_logic; en_x10: out std_logic; en_x11: out std_logic; en_x12: out std_logic; en_x13: out std_logic; en_x14: out std_logic; en_x15: out std_logic; en_x16: out std_logic; en_x17: out std_logic; en_x18: out std_logic; en_x19: out std_logic; en_x2: out std_logic; en_x20: out std_logic; en_x21: out std_logic; en_x22: out std_logic; en_x23: out std_logic; en_x24: out std_logic; en_x25: out std_logic; en_x26: out std_logic; en_x27: out std_logic; en_x28: out std_logic; en_x29: out std_logic; en_x3: out std_logic; en_x30: out std_logic; en_x31: out std_logic; en_x32: out std_logic; en_x4: out std_logic; en_x5: out std_logic; en_x6: out std_logic; en_x7: out std_logic; en_x8: out std_logic; en_x9: out std_logic; reg01_rd: out std_logic_vector(31 downto 0); reg01_rv: out std_logic; reg02_rd: out std_logic_vector(31 downto 0); reg02_rv: out std_logic; reg03_rd: out std_logic_vector(31 downto 0); reg03_rv: out std_logic; reg04_rd: out std_logic_vector(31 downto 0); reg04_rv: out std_logic; reg05_rd: out std_logic_vector(31 downto 0); reg05_rv: out std_logic; reg06_rd: out std_logic_vector(31 downto 0); reg06_rv: out std_logic; reg07_rd: out std_logic_vector(31 downto 0); reg07_rv: out std_logic; reg08_rd: out std_logic_vector(31 downto 0); reg08_rv: out std_logic; reg09_rd: out std_logic_vector(31 downto 0); reg09_rv: out std_logic; reg10_rd: out std_logic_vector(31 downto 0); reg10_rv: out std_logic; reg11_rd: out std_logic_vector(31 downto 0); reg11_rv: out std_logic; reg12_rd: out std_logic_vector(31 downto 0); reg12_rv: out std_logic; reg13_rd: out std_logic_vector(31 downto 0); reg13_rv: out std_logic; reg14_rd: out std_logic_vector(31 downto 0); reg14_rv: out std_logic ); end inout_logic; architecture structural of inout_logic is attribute core_generation_info: string; attribute core_generation_info of structural : architecture is "PCIe_UserLogic_00,sysgen_core,{clock_period=5.00000000,clocking=Clock_Enables,compilation=NGC_Netlist,sample_periods=1.00000000000,testbench=0,total_blocks=351,xilinx_chipscope_block=1,xilinx_constant_block_block=23,xilinx_counter_block=1,xilinx_gateway_in_block=44,xilinx_gateway_out_block=39,xilinx_inverter_block=2,xilinx_logical_block_block=1,xilinx_register_block=89,xilinx_shared_memory_based_from_register_block=62,xilinx_shared_memory_based_to_register_block=62,xilinx_subsystem_generator_block=1,xilinx_system_generator_block=2,xilinx_type_converter_block=14,}"; signal constant1_op_net_x0: std_logic; signal constant5_op_net_x0: std_logic; signal debug_in_1i_net: std_logic_vector(31 downto 0); signal debug_in_2i_net: std_logic_vector(31 downto 0); signal debug_in_3i_net: std_logic_vector(31 downto 0); signal debug_in_4i_net: std_logic_vector(31 downto 0); signal dma_host2board_busy_net: std_logic; signal dma_host2board_done_net: std_logic; signal from_register10_data_out_net: std_logic_vector(31 downto 0); signal from_register11_data_out_net: std_logic_vector(31 downto 0); signal from_register12_data_out_net: std_logic; signal from_register13_data_out_net: std_logic_vector(31 downto 0); signal from_register14_data_out_net: std_logic; signal from_register15_data_out_net: std_logic_vector(31 downto 0); signal from_register16_data_out_net: std_logic; signal from_register17_data_out_net: std_logic_vector(31 downto 0); signal from_register18_data_out_net: std_logic; signal from_register19_data_out_net: std_logic_vector(31 downto 0); signal from_register1_data_out_net: std_logic; signal from_register20_data_out_net: std_logic; signal from_register21_data_out_net: std_logic_vector(31 downto 0); signal from_register22_data_out_net: std_logic; signal from_register23_data_out_net: std_logic_vector(31 downto 0); signal from_register24_data_out_net: std_logic; signal from_register25_data_out_net: std_logic_vector(31 downto 0); signal from_register26_data_out_net: std_logic; signal from_register27_data_out_net: std_logic_vector(31 downto 0); signal from_register28_data_out_net: std_logic; signal from_register2_data_out_net: std_logic; signal from_register3_data_out_net: std_logic_vector(31 downto 0); signal from_register4_data_out_net: std_logic; signal from_register5_data_out_net: std_logic_vector(31 downto 0); signal from_register6_data_out_net: std_logic; signal from_register7_data_out_net: std_logic_vector(31 downto 0); signal from_register8_data_out_net: std_logic_vector(31 downto 0); signal from_register9_data_out_net: std_logic; signal reg01_td_net: std_logic_vector(31 downto 0); signal reg01_tv_net: std_logic; signal reg02_td_net: std_logic_vector(31 downto 0); signal reg02_tv_net: std_logic; signal reg03_td_net: std_logic_vector(31 downto 0); signal reg03_tv_net: std_logic; signal reg04_td_net: std_logic_vector(31 downto 0); signal reg04_tv_net: std_logic; signal reg05_td_net: std_logic_vector(31 downto 0); signal reg05_tv_net: std_logic; signal reg06_td_net: std_logic_vector(31 downto 0); signal reg06_tv_net: std_logic; signal reg07_td_net: std_logic_vector(31 downto 0); signal reg07_tv_net: std_logic; signal reg08_td_net: std_logic_vector(31 downto 0); signal reg08_tv_net: std_logic; signal reg09_td_net: std_logic_vector(31 downto 0); signal reg09_tv_net: std_logic; signal reg10_td_net: std_logic_vector(31 downto 0); signal reg10_tv_net: std_logic; signal reg11_td_net: std_logic_vector(31 downto 0); signal reg11_tv_net: std_logic; signal reg12_td_net: std_logic_vector(31 downto 0); signal reg12_tv_net: std_logic; signal reg13_td_net: std_logic_vector(31 downto 0); signal reg13_tv_net: std_logic; signal reg14_td_net: std_logic_vector(31 downto 0); signal reg14_tv_net: std_logic; begin from_register1_data_out_net <= data_out; from_register10_data_out_net <= data_out_x0; from_register11_data_out_net <= data_out_x1; from_register2_data_out_net <= data_out_x10; from_register20_data_out_net <= data_out_x11; from_register21_data_out_net <= data_out_x12; from_register22_data_out_net <= data_out_x13; from_register23_data_out_net <= data_out_x14; from_register24_data_out_net <= data_out_x15; from_register25_data_out_net <= data_out_x16; from_register26_data_out_net <= data_out_x17; from_register27_data_out_net <= data_out_x18; from_register28_data_out_net <= data_out_x19; from_register12_data_out_net <= data_out_x2; from_register3_data_out_net <= data_out_x20; from_register4_data_out_net <= data_out_x21; from_register5_data_out_net <= data_out_x22; from_register6_data_out_net <= data_out_x23; from_register7_data_out_net <= data_out_x24; from_register8_data_out_net <= data_out_x25; from_register9_data_out_net <= data_out_x26; from_register13_data_out_net <= data_out_x3; from_register14_data_out_net <= data_out_x4; from_register15_data_out_net <= data_out_x5; from_register16_data_out_net <= data_out_x6; from_register17_data_out_net <= data_out_x7; from_register18_data_out_net <= data_out_x8; from_register19_data_out_net <= data_out_x9; debug_in_1i_net <= debug_in_1i; debug_in_2i_net <= debug_in_2i; debug_in_3i_net <= debug_in_3i; debug_in_4i_net <= debug_in_4i; dma_host2board_busy_net <= dma_host2board_busy; dma_host2board_done_net <= dma_host2board_done; reg01_td_net <= reg01_td; reg01_tv_net <= reg01_tv; reg02_td_net <= reg02_td; reg02_tv_net <= reg02_tv; reg03_td_net <= reg03_td; reg03_tv_net <= reg03_tv; reg04_td_net <= reg04_td; reg04_tv_net <= reg04_tv; reg05_td_net <= reg05_td; reg05_tv_net <= reg05_tv; reg06_td_net <= reg06_td; reg06_tv_net <= reg06_tv; reg07_td_net <= reg07_td; reg07_tv_net <= reg07_tv; reg08_td_net <= reg08_td; reg08_tv_net <= reg08_tv; reg09_td_net <= reg09_td; reg09_tv_net <= reg09_tv; reg10_td_net <= reg10_td; reg10_tv_net <= reg10_tv; reg11_td_net <= reg11_td; reg11_tv_net <= reg11_tv; reg12_td_net <= reg12_td; reg12_tv_net <= reg12_tv; reg13_td_net <= reg13_td; reg13_tv_net <= reg13_tv; reg14_td_net <= reg14_td; reg14_tv_net <= reg14_tv; data_in <= debug_in_2i_net; data_in_x0 <= reg04_tv_net; data_in_x1 <= reg04_td_net; data_in_x10 <= debug_in_3i_net; data_in_x11 <= debug_in_4i_net; data_in_x12 <= reg09_tv_net; data_in_x13 <= reg09_td_net; data_in_x14 <= reg10_tv_net; data_in_x15 <= reg10_td_net; data_in_x16 <= reg08_tv_net; data_in_x17 <= reg08_td_net; data_in_x18 <= reg11_tv_net; data_in_x19 <= reg11_td_net; data_in_x2 <= reg05_tv_net; data_in_x20 <= reg12_tv_net; data_in_x21 <= reg01_tv_net; data_in_x22 <= reg12_td_net; data_in_x23 <= reg13_tv_net; data_in_x24 <= reg13_td_net; data_in_x25 <= reg14_tv_net; data_in_x26 <= reg14_td_net; data_in_x27 <= reg02_tv_net; data_in_x28 <= reg02_td_net; data_in_x29 <= debug_in_1i_net; data_in_x3 <= reg05_td_net; data_in_x30 <= reg01_td_net; data_in_x31 <= reg03_tv_net; data_in_x32 <= reg03_td_net; data_in_x4 <= reg06_tv_net; data_in_x5 <= reg06_td_net; data_in_x6 <= reg07_tv_net; data_in_x7 <= reg07_td_net; data_in_x8 <= dma_host2board_busy_net; data_in_x9 <= dma_host2board_done_net; en <= constant5_op_net_x0; en_x0 <= constant5_op_net_x0; en_x1 <= constant5_op_net_x0; en_x10 <= constant5_op_net_x0; en_x11 <= constant5_op_net_x0; en_x12 <= constant1_op_net_x0; en_x13 <= constant1_op_net_x0; en_x14 <= constant1_op_net_x0; en_x15 <= constant1_op_net_x0; en_x16 <= constant1_op_net_x0; en_x17 <= constant1_op_net_x0; en_x18 <= constant1_op_net_x0; en_x19 <= constant1_op_net_x0; en_x2 <= constant5_op_net_x0; en_x20 <= constant1_op_net_x0; en_x21 <= constant5_op_net_x0; en_x22 <= constant1_op_net_x0; en_x23 <= constant1_op_net_x0; en_x24 <= constant1_op_net_x0; en_x25 <= constant1_op_net_x0; en_x26 <= constant1_op_net_x0; en_x27 <= constant5_op_net_x0; en_x28 <= constant5_op_net_x0; en_x29 <= constant5_op_net_x0; en_x3 <= constant5_op_net_x0; en_x30 <= constant5_op_net_x0; en_x31 <= constant5_op_net_x0; en_x32 <= constant5_op_net_x0; en_x4 <= constant5_op_net_x0; en_x5 <= constant5_op_net_x0; en_x6 <= constant5_op_net_x0; en_x7 <= constant5_op_net_x0; en_x8 <= constant5_op_net_x0; en_x9 <= constant5_op_net_x0; reg01_rd <= from_register3_data_out_net; reg01_rv <= from_register1_data_out_net; reg02_rd <= from_register5_data_out_net; reg02_rv <= from_register2_data_out_net; reg03_rd <= from_register7_data_out_net; reg03_rv <= from_register6_data_out_net; reg04_rd <= from_register8_data_out_net; reg04_rv <= from_register4_data_out_net; reg05_rd <= from_register10_data_out_net; reg05_rv <= from_register9_data_out_net; reg06_rd <= from_register11_data_out_net; reg06_rv <= from_register12_data_out_net; reg07_rd <= from_register13_data_out_net; reg07_rv <= from_register14_data_out_net; reg08_rd <= from_register15_data_out_net; reg08_rv <= from_register16_data_out_net; reg09_rd <= from_register17_data_out_net; reg09_rv <= from_register18_data_out_net; reg10_rd <= from_register19_data_out_net; reg10_rv <= from_register20_data_out_net; reg11_rd <= from_register21_data_out_net; reg11_rv <= from_register22_data_out_net; reg12_rd <= from_register23_data_out_net; reg12_rv <= from_register24_data_out_net; reg13_rd <= from_register25_data_out_net; reg13_rv <= from_register26_data_out_net; reg14_rd <= from_register27_data_out_net; reg14_rv <= from_register28_data_out_net; constant1: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => constant1_op_net_x0 ); constant5: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => constant5_op_net_x0 ); end structural;