URL
https://opencores.org/ocsvn/plb2wbbridge/plb2wbbridge/trunk
Subversion Repositories plb2wbbridge
[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [32bit_on_128bitPLB_asyn/] [simulation/] [test_cases/] [simple_line_rw/] [transfers.bfl] - Rev 2
Compare with Previous | Blame | View Log
set_alias(PART = 1)set_alias(SUBPART = 2)set_alias(SUBSUBPART = 3)----------------------------------- 32-Bit Master --set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)configure(msize=00)mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)mem_update(addr=f1000000,data=01000000_02000000_03000000_04000000)wait( level=PART )write ( addr=f0000000, size=0010, be=1111111111111111 )wait ( level=SUBSUBPART )wait ( level=SUBSUBPART )write ( addr=f1000000, size=0001, be=1111111111111111 )wait ( level=SUBSUBPART )read ( addr=f0000000, size=0010, be=1111111111111111 )wait ( level=SUBSUBPART )wait ( level=SUBSUBPART )read ( addr=f1000000, size=0001, be=1111111111111111 )----------------------------------- 64-Bit Master --set_device(path=/system_tb/dut/plb_bfm_master_64/plb_bfm_master_64/master,device_type=plb_master)configure(msize=01)mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)mem_update(addr=f1000000,data=01000000_02000000_03000000_04000000)wait( level=PART )wait( level=SUBPART )wait( level=SUBPART )write ( addr=f0000000, size=0010, be=1111111111111111 )wait ( level=SUBSUBPART )write ( addr=f1000000, size=0001, be=1111111111111111 )wait ( level=SUBSUBPART )read ( addr=f0000000, size=0010, be=1111111111111111 )wait ( level=SUBSUBPART )wait ( level=SUBSUBPART )read ( addr=f1000000, size=0001, be=1111111111111111 )----------------------------------- 128-Bit Master --set_device(path=/system_tb/dut/plb_bfm_master_128/plb_bfm_master_128/master,device_type=plb_master)configure(msize=10)mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)mem_update(addr=f0000010,data=01111111_02111111_03111111_04111111)mem_update(addr=f1000000,data=01000000_02000000_03000000_04000000)wait( level=PART )wait( level=SUBPART )wait( level=SUBPART )wait( level=SUBPART )write ( addr=f0000000, size=0010, be=1111111111111111 )wait ( level=SUBSUBPART )write ( addr=f1000000, size=0001, be=1111111111111111 )wait ( level=SUBSUBPART )read ( addr=f0000000, size=0010, be=1111111111111111 )wait ( level=SUBSUBPART )wait ( level=SUBSUBPART )read ( addr=f1000000, size=0001, be=1111111111111111 )