Subversion Repositories plb2wbbridge

 set_alias(PART         = 1)
 set_alias(SUBPART      = 2)
 set_alias(SUBSUBPART   = 3)
 
 
 ---------------------------------
 --  32-Bit Master              --
 
 set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
 configure(msize=00)
 mem_update(addr=00010000,data=00000000_00000000_00000000_00000000)  
 mem_update(addr=00010010,data=00000000_00000000_00000000_00000000)  
 

 mem_update(addr=f0000000,data=11000001_11000002_11000003_11000004)
 mem_update(addr=f0000010,data=11111111_11111112_11111113_11111114)
 mem_update(addr=f0000020,data=11222221_11222222_11222223_11222224)
 mem_update(addr=f0000030,data=11333331_11333332_11333333_11333334)

 mem_update(addr=f1000000,data=22000001_22000002_22000003_22000004)
 mem_update(addr=f1000010,data=22111111_22111112_22111113_22111114)
 mem_update(addr=f1000020,data=22222221_22222222_22222223_22222224)
 mem_update(addr=f1000030,data=22333331_22333332_22333333_22333334)

 mem_update(addr=f2000000,data=33000001_33000002_33000003_33000004)
 mem_update(addr=f2000010,data=33111111_33111112_33111113_33111114)
 mem_update(addr=f2000020,data=33222221_33222222_33222223_33222224)
 mem_update(addr=f2000030,data=33333331_33333332_33333333_33333334)


 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 

 write   ( addr=f0000000, size=0000, be=1111 )
 write   ( addr=f0000004, size=0000, be=1111 )
 -- we will get an error on wb-side after two successful writes
 write   ( addr=f0000008, size=0000, be=1111 )
 


 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 -- we're now checking the status registers:
 mem_update( addr=00010000, data=20000000 )
 mem_update( addr=00010004, data=11000003 )
 mem_update( addr=00010008, data=f0000008 )
 read  ( addr=00010000, size=0001, be=1111 )
 read  ( addr=00010004, size=0000, be=1111 )
 read  ( addr=00010008, size=0000, be=1111 )

 -- we have to clear the exception
 mem_update( addr=00010000, data=00000000 )
 write   ( addr=00010000, size=0000, be=1111 )

 -- we abort the transfer
 write   ( addr=00010008, size=0000, be=1111 )
 
 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 

 ------------------

 write   ( addr=f0000000, size=0001, be=1111 )
 -- we wait (this simulates the interrupt-latency)
 -- and continue the transfer
 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 write   ( addr=00010004, size=0000, be=1111 )
 -- we have to clear the exception
 write   ( addr=00010000, size=0000, be=1111 )


 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 

 --------------------
 
 
 write   ( addr=f1000000, size=0001, be=1111 )
 -- we wait (this simulates the interrupt-latency)
 -- and continue the transfer
 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 write   ( addr=00010004, size=0000, be=1111 )
 -- we have to clear the exception
 write   ( addr=00010000, size=0000, be=1111 )



 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 

 --------------------
 
 
  write   ( addr=f2000000, size=0010, be=1111 )
  -- we wait (this simulates the interrupt-latency)
  -- and continue the transfer
  wait( level=SUBSUBPART )
  wait( level=SUBSUBPART )
  wait( level=SUBSUBPART )
  wait( level=SUBSUBPART )
  write   ( addr=00010004, size=0000, be=1111 )
 -- we have to clear the exception
  write   ( addr=00010000, size=0000, be=1111 )




 -- this causes several address-pipelining situations
 read    ( addr=f1000000, size=0000, be=1111 )
 read    ( addr=f2000000, size=0000, be=1111 )
 read    ( addr=f2000000, size=0001, be=1111 )
 read    ( addr=f1000000, size=0000, be=1111 )
 read    ( addr=f1000000, size=1010, be=0011 )
 read    ( addr=f2000000, size=1010, be=0011 )
 read    ( addr=f2000000, size=0001, be=1111 )
 read    ( addr=f1000000, size=1010, be=0010 )
 read    ( addr=f2000000, size=0000, be=1111 )
 read    ( addr=f2000000, size=1010, be=0001 )

 
 wait( level=SUBPART )
 wait( level=SUBPART )

 -- we're now checking the status registers:
 mem_update( addr=00010000, data=40000000 )
 read  ( addr=00010000, size=0000, be=1111 )
 mem_update( addr=00010000, data=00000000 )

 -- clear the interrupt
 write   ( addr=00010000, size=0000, be=1111 )