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[/] [powersupplysequencer/] [vhdl/] [msi/] [retrigg_timer/] [retrigg_timer_tb.vhd] - Rev 2

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-- (c) 2005..2010 Gerhard Hoffmann opencores@hoffmann-hochfrequenz.de
.. V1.0 published under BSD license
----------------------------------------------------------------------------------------------------
-- Tool versions:   Modelsim, ISE 6 .. 10
-- Description:     testbed for retriggerable timer
 
-- calls lib:       ieee standard
-- calls entities:  clk_rst, retrigg_timer
----------------------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
 
entity retrigg_timer_tb is begin end retrigg_timer_tb;
 
 
architecture tb of retrigg_timer_tb is
 
  signal rst, clk: std_logic;
  signal do, done, running: std_logic;
 
begin
 
 
 
u_clk_rst: entity work.clk_rst
 
  generic  map(
    verbose           => false,
    clock_frequency   => 100.0e6,
    min_resetwidth    => 46 ns
  )
 
  port map( 
    clk               => clk,
    rst               => rst
  );  
 
 
 
do <= '0',
      '1' after  95 ns, '0' after 105 ns,  -- trigger first time
      '1' after 205 ns, '0' after 215 ns,  -- trigger second time
      '1' after 245 ns, '0' after 255 ns;  -- and once more to test retrigger
 
 
 
uut: entity work.retrigg_timer
 
  generic map (
    ticks     => 5
  )
 
  port map (
    clk       => clk,
    rst       => rst,
 
    do        => do,
    done      => done,
    running   => running
  );
 
 
end tb;
 
 
 

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