Subversion Repositories priority_encoder

$date
        Thu Sep 10 19:55:20 2015
$end
$version
        Icarus Verilog
$end
$timescale
        100ps
$end
$scope module testbench $end
$var wire 7 ! out_data [6:0] $end
$var wire 128 " in_data_wbs [127:0] $end
$var wire 128 # in_data [127:0] $end
$var reg 128 $ in_vect [127:0] $end
$var integer 32 % i [31:0] $end
$scope module bs0 $end
$var wire 128 & in [127:0] $end
$var wire 128 ' out_rev [127:0] $end
$var wire 128 ( out [127:0] $end
$var wire 128 ) in_rev [127:0] $end
$scope begin bl_generation_h[0] $end
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$scope begin bl_generation_h[28] $end
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$scope begin bl_generation_h[127] $end
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$var wire 128 * in [127:0] $end
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#0
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