Subversion Repositories product_code_iterative_decoder

-- ------------------------------------------------------------------------
-- Copyright (C) 2005 Arif Endro Nugroho
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-- 1. Redistributions of source code must retain the above copyright
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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library IEEE;
use IEEE.std_logic_1164.ALL;
 
entity ser2par8bit is
   port (
     clock : in  bit;
     clear : in  bit;
     start : in  bit;
     rxin  : in  bit_vector (07 downto 00);
     y0    : out bit_vector (07 downto 00);
     y1    : out bit_vector (07 downto 00);
     y2    : out bit_vector (07 downto 00);
     y3    : out bit_vector (07 downto 00);
     r0    : out bit_vector (07 downto 00);
     r1    : out bit_vector (07 downto 00);
     c0    : out bit_vector (07 downto 00);
     c1    : out bit_vector (07 downto 00)
     );
end ser2par8bit;
 
architecture data_flow of ser2par8bit is
 
subtype type_word is bit_vector (07 downto 00);
type type_fifo is array (09 downto 00) of type_word;
signal fifo8bx7 : type_fifo;
 
begin
 
process (clock, clear)
begin
    if (clear = '1') then
        fifo8bx7 (00) <= (others => '0');
        fifo8bx7 (01) <= (others => '0');
        fifo8bx7 (02) <= (others => '0');
        fifo8bx7 (03) <= (others => '0');
        fifo8bx7 (04) <= (others => '0');
        fifo8bx7 (05) <= (others => '0');
        fifo8bx7 (06) <= (others => '0');
        fifo8bx7 (07) <= (others => '0');
        fifo8bx7 (08) <= (others => '0');
        fifo8bx7 (09) <= (others => '0');
    elsif ((clock = '0') and clock'event) then
	fifo8bx7 (00) <= rxin (07 downto 00);
	fifo8bx7 (09 downto 01) <= fifo8bx7 (08 downto 00);
    end if;
end process;
 
process (start)
begin
    if (start = '0' and start'event) then
        y0 <= fifo8bx7 (08);
        y1 <= fifo8bx7 (07);
        y2 <= fifo8bx7 (06);
        y3 <= fifo8bx7 (05);
        r0 <= fifo8bx7 (04);
        r1 <= fifo8bx7 (03);
        c0 <= fifo8bx7 (02);
        c1 <= fifo8bx7 (01);
   end if;
end process;
 
end data_flow;