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[/] [pwm_with_dithering/] [trunk/] [src/] [pwm_ineq.vhd] - Rev 3
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---------------------------------------------------------------------------------- -- Company: Aboa Space Research Oy (ASRO) -- Engineer: Tero Säntti -- -- Create Date: 15:31:34 01/27/2021 -- Design Name: PWM -- Module Name: pwm_ineq - Behavioral -- Target Devices: None / non-specific -- Tool versions: None / non-specific -- Description: Dithered PWM. Cycle ends with inequality operation. Clock -- frequency is not maximal. Not sensitive to input -- changes during operation. -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity pwm_ineq is Generic ( bits: integer:=16; dithering:integer:=5 ); Port ( clk : in STD_LOGIC; set : in STD_LOGIC_VECTOR(bits-1 downto 0); o : out STD_LOGIC); end pwm_ineq; architecture Behavioral of pwm_ineq is signal o_i:std_logic:='0'; signal cnt:std_logic_vector(bits-1 downto 0):=(others => '0'); signal zeros:std_logic_vector((bits-dithering)-1 downto 0):=(others => '0'); signal target:std_logic_vector((bits-dithering) downto 0); signal reversed_cnt_top:std_logic_vector((dithering)-1 downto 0); signal inc:std_logic; function reverse_and_rebase_bit_order(a: in std_logic_vector) return std_logic_vector is variable result: std_logic_vector(a'high-a'low downto 0); begin for i in a'RANGE loop result(a'high-i) := a(i); end loop; return result; end; begin -- output mapping: o <= o_i; zeros <= (others => '0'); normal: if dithering = 0 generate doit:process(clk) begin if rising_edge(clk) then cnt <= cnt + 1; o_i <= o_i; if cnt=zeros then o_i <= '1'; end if; if cnt>=set then o_i <= '0'; end if; end if; end process; end generate; dithered: if dithering > 0 generate reversed_cnt_top <= reverse_and_rebase_bit_order(cnt(bits-1 downto bits-dithering)); inc <= '1' when (reversed_cnt_top < set(dithering-1 downto 0)) else '0'; target <= ('0' & set(bits-1 downto dithering)) + inc; doit:process(clk) begin if rising_edge(clk) then cnt <= cnt + 1; o_i <= o_i; if cnt((bits-dithering)-1 downto 0) = zeros then o_i <= '1'; end if; if ('0' & cnt((bits-dithering)-1 downto 0)) >= target then o_i <= '0'; end if; end if; end process; end generate; end Behavioral;