Subversion Repositories pwm_with_dithering

--------------------------------------------------------------------------------
-- Company: 		Aboa Space Research Oy (ASRO)
-- Engineer:		Tero Säntti
--
-- Create Date:   14:58:12 01/27/2021
-- Design Name:   PWM test top
-- Project Name:  PWM
-- Target Device: None / Simulation ONLY
-- Tool versions: None / non-specific
-- Description:   Very generic testbench for pwm
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY test_top IS
	generic(
		bits		:integer:=16;
		vdd		:real:=3.3;
		dithering:integer:=5
	);
END test_top;
 
ARCHITECTURE behavior OF test_top IS 
 
 
COMPONENT pwm
    Generic ( 
				bits: integer:=16;
				dithering:integer:=5
				);
    PORT(
         clk : IN  std_logic;
         set : IN  std_logic_vector(bits-1 downto 0);
         o : OUT  std_logic
        );
END COMPONENT;
 
COMPONENT pwm_pipelined
    Generic ( 
				bits: integer:=16;
				dithering:integer:=5
				);
    PORT(
         clk : IN  std_logic;
         set : IN  std_logic_vector(bits-1 downto 0);
         o : OUT  std_logic
        );
END COMPONENT;
 
COMPONENT pwm_pipelined_small
    Generic ( 
				bits: integer:=16;
				dithering:integer:=5
				);
    PORT(
         clk : IN  std_logic;
         set : IN  std_logic_vector(bits-1 downto 0);
         o : OUT  std_logic
        );
END COMPONENT;
 
COMPONENT pwm_ineq
    Generic ( 
				bits: integer:=16;
				dithering:integer:=5
				);
    PORT(
         clk : IN  std_logic;
         set : IN  std_logic_vector(bits-1 downto 0);
         o : OUT  std_logic
        );
END COMPONENT;
 
COMPONENT pwm_reg
    Generic ( 
				bits: integer:=16;
				dithering:integer:=5
				);
    PORT(
         clk : IN  std_logic;
         set : IN  std_logic_vector(bits-1 downto 0);
         o : OUT  std_logic
        );
END COMPONENT;
 
component pwm_to_voltage is
    Generic ( 
				autorefresh_interval : time;
				autorefresh_enabled : boolean;
				supply_voltage : real:=3.3;
				R : real:=100.0;
				C : real:=0.0001
				);
    Port ( pwm : in  STD_LOGIC;
           voltage : out real;
			  frequency : out real
			  );
end component;
 
 
component rc_filter is
    Generic ( 
				autorefresh_interval : time;
				autorefresh_enabled : boolean;
				supply_voltage : real:=3.3;
				R : real:=100.0;
				C : real:=0.0001
				);
    Port ( v_in : in  real;
           v_out : out real
			  );
end component;
 
component pseudo_ADC is
    Generic ( 
				bits : integer :=bits;
				supply_voltage : real:=3.3
				);
    Port ( v_in : in  real;
			  digital_out : out std_logic_vector(bits-1 downto 0)
			  );
end component;
 
component analyzer is
    Generic ( 
				supply_voltage : real:=3.3;
				filter_strength: real:=0.99
				);
    Port ( enable : in std_logic;
			  v_in : in  real;
           v_out : buffer real;
			  v_max : buffer real;
			  v_min : buffer real;
			  v_p2p : out real
			  );
end component;	 
 
   --Inputs
   signal clk : std_logic := '0';
   signal set : std_logic_vector(bits-1 downto 0) := (others => '0');
 
 	--Outputs
   signal o : std_logic;
 
	signal volts:real;
	signal frequency:real;
	signal filtered_volts:real;
   signal read_back : std_logic_vector(bits-1 downto 0);
	signal analyzed_volts: real;
	signal analyzed_min: real;
	signal analyzed_max: real;
	signal analyzed_p2p: real;
	signal analyzer_enable: std_logic;
 
   -- Clock period definitions
   constant clk_period : time := 8.3333333 ns; -- AKA 120MHz
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: pwm_pipelined_small
    Generic map( 
				bits		 => bits,
				dithering => dithering
				)
	 PORT MAP (
          clk => clk,
          set => set,
          o => o
        );
 
   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 
   -- Stimulus process (Set your test patterns here, or make a more automated test structure as needed)
	-- This is set for running 100ms.
   stim_proc: process
   begin		
		analyzer_enable <= '0';
      set <= "1000000000010000";
		wait for 30 ms;
		analyzer_enable <= '1';		
		wait for 20 ms;
		analyzer_enable <= '0';
      set <= "0010111001000101";
		wait for 30 ms;
		analyzer_enable <= '1';	
      wait;
   end process;
 
voltage_generator: pwm_to_voltage
    Generic map( 
				autorefresh_interval => 0.1 us,--: time;
				autorefresh_enabled  => true,--: boolean;
				supply_voltage 		=> vdd,--: real:=3.3;
				R 							=> 100000.0,-- 100k
				C 							=> 0.000000018 -- 18n 
				)
    Port map( 
				pwm 		 => o,--: in  STD_LOGIC;
				voltage 	 => volts,--: out real;
			   frequency => frequency--: out real
				);
 
Secondary_RC_filter: rc_filter 
    Generic map( 
				autorefresh_interval => 1 us,--: time;
				autorefresh_enabled  => false,--: boolean; -- IF previous stages are set to update often, then this can be false
				supply_voltage 		=> vdd,--: real:=3.3;
				R 							=> 100.0,--: real:=100.0; 0.1k
				C 							=> 0.000000200 -- 200n
				)
    Port map( 
				v_in 			=> volts,--: in  real;
            v_out			=> filtered_volts--: out real;
			   );
 
Output_analyzer: analyzer 
    Generic map( 
				supply_voltage  => vdd,--: real:=3.3;
				filter_strength => 0.999--: real:=0.99
				)
    Port map( 
				enable => analyzer_enable,--: in std_logic;
			   v_in 	 => filtered_volts,--: in  real;
            v_out  => analyzed_volts,--: buffer real;
			   v_max  => analyzed_max,--: buffer real;
			   v_min  => analyzed_min,--: buffer real;
			   v_p2p  => analyzed_p2p--: out real
			  );
 
read_back_ADC:pseudo_ADC
    Generic map( 
				bits 				=> bits,--: integer :=16;
				supply_voltage => vdd--: real:=3.3
				)
    Port map( 
				v_in => analyzed_volts,--: in  real;
			   digital_out => read_back--: out std_logic_vector(bits-1 downto 0)
			  );
 
 
END;