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[/] [qaz_libs/] [trunk/] [PCIe/] [sim/] [tests/] [tb_riffa_register_file/] [tb_riffa_register_file.sv] - Rev 40

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////


module tb_top();

  // --------------------------------------------------------------------
  // test bench clock & reset
  wire clk_100mhz;
  wire tb_clk = clk_100mhz;
  wire tb_rst;

  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);


  // --------------------------------------------------------------------
  //
  wire clk = tb_clk;
  wire reset;

  sync_reset sync_reset_i(tb_clk, tb_rst, reset);


  // --------------------------------------------------------------------
  //
  import tb_riffa_register_file_pkg::*;


  // --------------------------------------------------------------------
  //
  riffa_chnl_if #(.N(N)) chnl_bus(.*);
  riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers


  // --------------------------------------------------------------------
  //
  riffa_register_file #(.N(N), .B(B))
    dut(.*);


  // --------------------------------------------------------------------
  // sim models
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // --------------------------------------------------------------------
  //
  for(genvar j = 0; j < r_if.RC; j++)
    assign r_if.register_in[j] = r_if.register_out[j];


  // --------------------------------------------------------------------
  //
  tb_riffa_register_file_class #(.N(N)) a_h;

  initial
    a_h = new(chnl_bus);


  // --------------------------------------------------------------------
  //
  int rx_count = 0;
  wire rx_en = chnl_bus.rx_data_valid & chnl_bus.rx_data_ren;

  always_ff @(posedge chnl_bus.rx_clk)
    if(chnl_bus.rx)
    begin
      if(rx_en)
        rx_count++;
    end
    else
      rx_count = 0;


  // --------------------------------------------------------------------
  //
  int tx_count = 0;
  wire tx_en = chnl_bus.tx_data_valid & chnl_bus.tx_data_ren;

  always_ff @(posedge chnl_bus.tx_clk)
    if(chnl_bus.tx)
    begin
      if(tx_en)
        tx_count++;
    end
    else
      tx_count = 0;



  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // sim models
  // --------------------------------------------------------------------



  // --------------------------------------------------------------------
  // test
  the_test test( tb_clk, tb_rst );

  initial
    begin

      test.run_the_test();

      $display("^^^---------------------------------");
      $display("^^^ %16.t | Testbench done.", $time);
      $display("^^^---------------------------------");

      $display("^^^---------------------------------");

      $stop();

    end

endmodule



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