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//////////////////////////////////////////////////////////////////////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////
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//////////////////////////////////////////////////////////////////////

module tb_top;
  import uvm_pkg::*;
  import tb_top_pkg::*;
  import riffa_pkg::*;
  `include "uvm_macros.svh"

  // --------------------------------------------------------------------
  wire clk_100mhz;
  wire tb_clk = clk_100mhz;
  wire tb_rst;
  wire clk_1000mhz;

  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);

  // --------------------------------------------------------------------
  wire clk = clk_100mhz;
  wire reset;

  sync_reset sync_reset_i(tb_clk, tb_rst, reset);

  // --------------------------------------------------------------------
  riffa_chnl_if #(N) chnl_bus(.*);
  riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers

  riffa_register_file #(.N(N), .B(B))
    dut(.*);

  // --------------------------------------------------------------------
  for(genvar j = 0; j < r_if.RC; j++)
    assign r_if.register_in[j] = r_if.register_out[j];

  // --------------------------------------------------------------------
  riffa_config #(N) cfg_h = new(chnl_bus);

  initial
  begin
    uvm_config_db #(riffa_config #(N))::set(null, "*", "riffa_config", cfg_h);
    run_test("t_debug");
  end

// --------------------------------------------------------------------
endmodule