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https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [PCIe_debug_if.sv] - Rev 42
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
interface
PCIe_debug_if
(
input reset,
input clk
);
logic [2:0] tlp_fmt;
logic [4:0] tlp_type;
logic [2:0] tlp_tc;
logic tlp_th;
logic tlp_td;
logic tlp_ep;
logic [2:0] tlp_attr;
logic tlp_at;
logic [9:0] tlp_length;
logic [1:0] tlp_ph;
logic enable_r;
logic [31:0] h0_r;
logic [31:0] h1_r;
logic [31:0] h2_r;
logic [31:0] h3_r;
logic tlp_is_3dw;
logic tlp_is_4dw;
logic [63:0] tlp_address;
// --------------------------------------------------------------------
//
endinterface
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