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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_axis_test_pattern.sv] - Rev 39

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//////////////////////////////////////////////////////////////////////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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//// This source file may be used and distributed without         ////
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//// removed from the file and that any derivative work contains  ////
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////                                                              ////
//// This source file is free software; you can redistribute it   ////
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//// later version.                                               ////
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//////////////////////////////////////////////////////////////////////


module
  riffa_axis_test_pattern
  #(
    N, // RIFFA data bus width in bytes
    W = 4, // word width in bytes
    WPB = N / W // number of words per beat
  )
  (
    riffa_chnl_if chnl_bus,
    input [31:0] tx_len,
    input clk,
    input reset
  );

  // --------------------------------------------------------------------
  //
  localparam I = 0; // TID width
  localparam D = 0; // TDEST width
  localparam U = 3; // TUSER width
  localparam RW = (N/4); // width of the RIFFA bus in 32 bit words


  // --------------------------------------------------------------------
  //
  wire aclk = clk;
  wire aresetn = ~reset;


  // --------------------------------------------------------------------
  //
  axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*);

  axis_test_patern #(.N(N), .W(W), .WPB(WPB))
    axis_test_patern_i(.*);


  // --------------------------------------------------------------------
  //
  wire tx_ready = 1;
  wire tx_last = 1;
  wire acked;
  wire [30:0] tx_off = 0;
  wire [30:0] tx_index;
  wire tx_done = (tx_index >= tx_len - RW);

  riffa_chn_tx #(.N(N))
    riffa_chn_tx_i(.*);


  // --------------------------------------------------------------------
  //
  assign axis_out.tready = chnl_bus.tx_data_ren & acked;


  // --------------------------------------------------------------------
  //
  assign chnl_bus.rx_clk = clk;
  assign chnl_bus.tx_clk = clk;
  assign chnl_bus.rx_reset = reset;
  assign chnl_bus.tx_reset = reset;
  assign chnl_bus.tx_last = tx_last;
  assign chnl_bus.tx_len = tx_len;
  assign chnl_bus.tx_off = tx_off;
  assign chnl_bus.tx_data_valid = axis_out.tvalid & acked;
  assign chnl_bus.tx_data = axis_out.tdata;

// --------------------------------------------------------------------
//
endmodule




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