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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_if.sv] - Rev 32

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////


interface
  riffa_chnl_if #(N); // data bus width in bytes

        wire              rx_clk;
        wire              rx_reset;
        wire              rx;
        wire              rx_ack;
        wire              rx_last;
        wire  [31:0]      rx_len;
        wire  [30:0]      rx_off;
        wire  [(8*N)-1:0] rx_data;
        wire              rx_data_valid;
        wire              rx_data_ren;

        wire              tx_clk;
        wire              tx_reset;
        wire              tx;
        wire              tx_ack;
        wire              tx_last;
        wire  [31:0]      tx_len;
        wire  [30:0]      tx_off;
        wire  [(8*N)-1:0] tx_data;
        wire              tx_data_valid;
        wire              tx_data_ren;


// --------------------------------------------------------------------
// synthesis translate_off

// from the RIFFA channel
  clocking cb_ep_rx @(posedge rx_clk);
    input rx;
    output rx_ack;
    input rx_last;
    input rx_len;
    input rx_off;
    input rx_data;
    input rx_data_valid;
    output rx_data_ren;
  endclocking

// from the RIFFA channel
  clocking cb_ep_tx @(posedge tx_clk);
    output tx;
    input tx_ack;
    output tx_last;
    output tx_len;
    output tx_off;
    output tx_data;
    output tx_data_valid;
    input tx_data_ren;
  endclocking

  // from the PCIe
  clocking cb_rp_tx @(posedge rx_clk);
    output rx;
    input rx_ack;
    output rx_last;
    output rx_len;
    output rx_off;
    output rx_data;
    output rx_data_valid;
    input rx_data_ren;
  endclocking

  // from the PCIe
  clocking cb_rp_rx @(posedge tx_clk);
    input tx;
    output tx_ack;
    input tx_last;
    input tx_len;
    input tx_off;
    input tx_data;
    input tx_data_valid;
    output tx_data_ren;
  endclocking
// synthesis translate_on
// --------------------------------------------------------------------


// --------------------------------------------------------------------
//
endinterface: riffa_chnl_if

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