OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_rx.sv] - Rev 43

Compare with Previous | Blame | View Log

//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////

module
  riffa_chn_rx
  #(
    N //  data bus width in bytes
  )
  (
    riffa_chnl_if chnl_bus,
    input rx_ready,
    output rx_done,
    output reg [30:0] rx_index,
    output reg rx_last,
    output reg [31:0] rx_len,
    output reg [30:0] rx_off,
    // output rx_data_ren, // shouldn't be here??
    output rd_empty,
    output [(8*N)-1:0] rd_data,
    input rd_en,

    input clk,
    input reset
  );

  // --------------------------------------------------------------------
  //
  riffa_chnl_rx_fsm
    riffa_chnl_rx_fsm_i
    (
      .rx(chnl_bus.rx),
      .rx_data_valid(chnl_bus.rx_data_valid),
      .rx_ack(chnl_bus.rx_ack),
      .*
    );


  // --------------------------------------------------------------------
  //
  always_ff @(posedge clk)
    if(chnl_bus.rx & chnl_bus.rx_ack)
    begin
      rx_last <= chnl_bus.rx_last;
      rx_len <= chnl_bus.rx_len;
      rx_off <= chnl_bus.rx_off;
    end


  // --------------------------------------------------------------------
  //
  wire [(8*N)-1:0] wr_data = chnl_bus.rx_data;
  wire wr_full;
  wire wr_en = chnl_bus.rx_data_ren & chnl_bus.rx_data_valid;

  tiny_sync_fifo #(.W((8*N)))
    tiny_sync_fifo_i(.*);


  // --------------------------------------------------------------------
  //
  always_ff @(posedge clk)
    if(reset | rx_done)
      rx_index <= 0;
    else if(rd_en)
      rx_index <= rx_index + (N/4); // increment by 32 bit words


  // --------------------------------------------------------------------
  //
  // assign rx_data_ren = ~wr_full; // shouldn't be here??
  assign chnl_bus.rx_data_ren = ~wr_full;


// --------------------------------------------------------------------
//
endmodule

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.