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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_rx_fsm.sv] - Rev 32

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
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//////////////////////////////////////////////////////////////////////

module
  riffa_chnl_rx_fsm
  (
    input   rx,
    input   rx_data_valid,
    output  rx_ack,
    output  rx_done,

    input   reset,
    input   clk
  );

  //---------------------------------------------------
  //  state machine binary definitions
  enum reg [4:0]
    {
      IDLE    = 5'b0_0001,
      ACK     = 5'b0_0010,
      RX      = 5'b0_0100,
      PENDING = 5'b0_1000,
      ERROR   = 5'b1_0000
    } state, next_state;


  //---------------------------------------------------
  //  state machine flop
  always_ff @(posedge clk)
    if(reset)
      state <= IDLE;
    else
      state <= next_state;


  //---------------------------------------------------
  //  state machine
  always_comb
    case(state)
      IDLE:     if(rx)
                  next_state <= ACK;
                else
                  next_state <= IDLE;

      ACK:      next_state <= RX;

      RX:       if(rx)
                  next_state <= RX;
                else if(rx_data_valid)
                  next_state <= PENDING;
                else
                  next_state <= IDLE;

      PENDING:  if(rx_data_valid)
                  next_state <= PENDING;
                else
                  next_state <= IDLE;

      ERROR:    next_state <= IDLE;

      default:  next_state <= ERROR;

    endcase


  // --------------------------------------------------------------------
  //
  assign rx_ack = (state == ACK);
  assign rx_done = (state != IDLE) & (next_state == IDLE);


// --------------------------------------------------------------------
//
endmodule

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