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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_tester.sv] - Rev 42

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
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//////////////////////////////////////////////////////////////////////

module
  riffa_chnl_tester
  #(
    C_PCI_DATA_WIDTH // Settings from Vivado IP Generator
  )
  (
    riffa_chnl_if chnl_bus,
    input clk,  // must be same clock domain as rx_clk & tx_clk
    input reset // must be same clock domain as rx_clk & tx_clk
  );

  // --------------------------------------------------------------------
  //
  chnl_tester #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
    chnl_tester_i
    (
      .CLK(clk),
      .RST(reset),    // riffa_reset includes riffa_endpoint resets
      // Rx interface
      .CHNL_RX_CLK(chnl_bus.rx_clk),
      .CHNL_RX(chnl_bus.rx),
      .CHNL_RX_ACK(chnl_bus.rx_ack),
      .CHNL_RX_LAST(chnl_bus.rx_last),
      .CHNL_RX_LEN(chnl_bus.rx_len),
      .CHNL_RX_OFF(chnl_bus.rx_off),
      .CHNL_RX_DATA(chnl_bus.rx_data),
      .CHNL_RX_DATA_VALID(chnl_bus.rx_data_valid),
      .CHNL_RX_DATA_REN(chnl_bus.rx_data_ren),
      // Tx interface
      .CHNL_TX_CLK(chnl_bus.tx_clk),
      .CHNL_TX(chnl_bus.tx),
      .CHNL_TX_ACK(chnl_bus.tx_ack),
      .CHNL_TX_LAST(chnl_bus.tx_last),
      .CHNL_TX_LEN(chnl_bus.tx_len),
      .CHNL_TX_OFF(chnl_bus.tx_off),
      .CHNL_TX_DATA(chnl_bus.tx_data),
      .CHNL_TX_DATA_VALID(chnl_bus.tx_data_valid),
      .CHNL_TX_DATA_REN(chnl_bus.tx_data_ren)
    );

// --------------------------------------------------------------------
//
endmodule

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