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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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//// This source file may be used and distributed without         ////
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//// removed from the file and that any derivative work contains  ////
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//// This source file is free software; you can redistribute it   ////
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//////////////////////////////////////////////////////////////////////


module
  riffa_chnl_w
  #(
    parameter C_NUM_CHNL,
    parameter C_PCI_DATA_WIDTH,
    parameter SIG_CHNL_LENGTH_W,
    parameter SIG_CHNL_OFFSET_W
  )
  (
    // RIFFA Interface Signals
    output  [C_NUM_CHNL-1:0]                      CHNL_RX_CLK, // Channel read clock
    input   [C_NUM_CHNL-1:0]                      CHNL_RX, // Channel read receive signal
    output  [C_NUM_CHNL-1:0]                      CHNL_RX_ACK, // Channel read received signal
    input   [C_NUM_CHNL-1:0]                      CHNL_RX_LAST, // Channel last read
    input   [(C_NUM_CHNL*SIG_CHNL_LENGTH_W)-1:0]  CHNL_RX_LEN, // Channel read length
    input   [(C_NUM_CHNL*SIG_CHNL_OFFSET_W)-1:0]  CHNL_RX_OFF, // Channel read offset
    input   [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_RX_DATA, // Channel read data
    input   [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_VALID, // Channel read data valid
    output  [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_REN, // Channel read data has been received

    output  [C_NUM_CHNL-1:0]                      CHNL_TX_CLK, // Channel write clock
    output  [C_NUM_CHNL-1:0]                      CHNL_TX, // Channel write receive signal
    input   [C_NUM_CHNL-1:0]                      CHNL_TX_ACK, // Channel write acknowledgment signal
    output  [C_NUM_CHNL-1:0]                      CHNL_TX_LAST, // Channel last write
    output  [(C_NUM_CHNL*SIG_CHNL_LENGTH_W)-1:0]  CHNL_TX_LEN, // Channel write length (in 32 bit words)
    output  [(C_NUM_CHNL*SIG_CHNL_OFFSET_W)-1:0]  CHNL_TX_OFF, // Channel write offset
    output  [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_TX_DATA, // Channel write data
    output  [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_VALID, // Channel write data valid
    input   [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_REN, // Channel write data has been received

    riffa_chnl_if chnl_bus[C_NUM_CHNL]
  );

  // --------------------------------------------------------------------
  //
  genvar i;
  generate
    for (i = 0; i < C_NUM_CHNL; i = i + 1)
    begin : channels
      assign CHNL_RX_CLK[i] = chnl_bus[i].rx_clk;
      assign chnl_bus[i].rx = CHNL_RX[i];
      assign CHNL_RX_ACK[i] = chnl_bus[i].rx_ack;
      assign chnl_bus[i].rx_last = CHNL_RX_LAST[i];
      assign chnl_bus[i].rx_len = CHNL_RX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W];
      assign chnl_bus[i].rx_off = CHNL_RX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W];
      assign chnl_bus[i].rx_data = CHNL_RX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH];
      assign chnl_bus[i].rx_data_valid = CHNL_RX_DATA_VALID[i];
      assign CHNL_RX_DATA_REN[i] = chnl_bus[i].rx_data_ren;

      assign CHNL_TX_CLK[i] = chnl_bus[i].tx_clk;
      assign CHNL_TX[i] = chnl_bus[i].tx;
      assign chnl_bus[i].tx_ack = CHNL_TX_ACK[i];
      assign CHNL_TX_LAST[i] = chnl_bus[i].tx_last;
      assign CHNL_TX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W] = chnl_bus[i].tx_len;
      assign CHNL_TX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W] = chnl_bus[i].tx_off;
      assign CHNL_TX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH] = chnl_bus[i].tx_data;
      assign CHNL_TX_DATA_VALID[i] = chnl_bus[i].tx_data_valid;
      assign chnl_bus[i].tx_data_ren = CHNL_TX_DATA_REN[i];
    end
  endgenerate


  // // --------------------------------------------------------------------
  // //
  // wire [C_NUM_CHNL-1:0]                     CHNL_RX_CLK;
  // wire [C_NUM_CHNL-1:0]                     CHNL_RX;
  // wire [C_NUM_CHNL-1:0]                     CHNL_RX_ACK;
  // wire [C_NUM_CHNL-1:0]                     CHNL_RX_LAST;
  // wire [(C_NUM_CHNL*32)-1:0]                CHNL_RX_LEN;
  // wire [(C_NUM_CHNL*31)-1:0]                CHNL_RX_OFF;
  // wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]  CHNL_RX_DATA;
  // wire [C_NUM_CHNL-1:0]                     CHNL_RX_DATA_VALID;
  // wire [C_NUM_CHNL-1:0]                     CHNL_RX_DATA_REN;
  // wire [C_NUM_CHNL-1:0]                     CHNL_TX_CLK;
  // wire [C_NUM_CHNL-1:0]                     CHNL_TX;
  // wire [C_NUM_CHNL-1:0]                     CHNL_TX_ACK;
  // wire [C_NUM_CHNL-1:0]                     CHNL_TX_LAST;
  // wire [(C_NUM_CHNL*32)-1:0]                CHNL_TX_LEN;
  // wire [(C_NUM_CHNL*31)-1:0]                CHNL_TX_OFF;
  // wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]  CHNL_TX_DATA;
  // wire [C_NUM_CHNL-1:0]                     CHNL_TX_DATA_VALID;
  // wire [C_NUM_CHNL-1:0]                     CHNL_TX_DATA_REN;


// --------------------------------------------------------------------
//
endmodule