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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_register_file.sv] - Rev 42
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module
riffa_register_file
#(
N, // data bus width in bytes
B // number of register banks
)
(
riffa_chnl_if chnl_bus,
riffa_register_if r_if,
input clk, // must be same clock domain as rx_clk & tx_clk
input reset // must be same clock domain as rx_clk & tx_clk
);
// --------------------------------------------------------------------
// synthesis translate_off
initial
begin
a_data_bus_mod: assert(N % 4 == 0) else $fatal;
a_data_bus_power_of_2: assert((N != 0) & ((N & (N - 1)) == 0)) else $fatal;
end
// synthesis translate_on
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
localparam RW = (N/4); // width of the bus in 32 bit words
localparam RC = RW * B; // number of available registers
// --------------------------------------------------------------------
//
wire rx_ready = ~reset;
wire rx_done;
wire [30:0] rx_index;
wire rx_last;
wire [31:0] rx_len;
wire [30:0] rx_off; // offset ignored, always start from offset 0
// wire rx_data_ren;
wire rd_empty;
wire [(8*N)-1:0] rd_data;
wire rd_en;
riffa_chn_rx #(.N(N))
riffa_chn_rx_i(.chnl_bus(chnl_bus), .*);
// --------------------------------------------------------------------
//
wire register_select [RC-1:0];
genvar j, k;
generate
for(j = 0; j < B; j = j + 1)
begin: register_j_gen
for(k = 0; k < RW; k = k + 1)
begin: register_k_gen
assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
assign r_if.wr_en[(j*RW) + k] = rd_en & register_select[(j*RW) + k];
always_ff @(posedge clk)
if(reset)
r_if.register_out[(j*RW) + k] <= 0;
else if(r_if.wr_en[(j*RW) + k])
r_if.register_out[(j*RW) + k] <= rd_data[k*32 +: 32];
end
end
endgenerate
// --------------------------------------------------------------------
//
// assign chnl_bus.rx_data_ren = rx_data_ren;
assign rd_en = ~rd_empty;
// --------------------------------------------------------------------
//
// write to register[0][0] to enable reading
wire tx_ready = r_if.wr_en[0] & rd_data[0];
wire tx_last = 1;
wire acked;
wire [31:0] tx_len = RC;
wire [30:0] tx_off = 0;
wire [30:0] tx_index;
wire tx_done = (tx_index >= chnl_bus.tx_len - RW);
riffa_chn_tx #(.N(N))
riffa_chn_tx_i(.*);
// --------------------------------------------------------------------
//
wire [(N*8)-1:0] data_in [(2 ** $clog2(B))-1:0];
generate
for(j = 0; j < B; j = j + 1)
begin: data_in_j_gen
for(k = 0; k < RW; k = k + 1)
begin: data_in_k_gen
assign data_in[j][k*32 +: 32] = r_if.register_out[(j*RW) + k];
end
end
endgenerate
// --------------------------------------------------------------------
//
recursive_mux #(.A($clog2(B)), .W(N*8))
recursive_mux_i
(
.select(tx_index[$clog2(B) + $clog2(RW) - 1:$clog2(RW)]),
.data_out(chnl_bus.tx_data),
.*
);
// --------------------------------------------------------------------
//
assign chnl_bus.rx_clk = clk;
assign chnl_bus.tx_clk = clk;
assign chnl_bus.rx_reset = reset;
assign chnl_bus.tx_reset = reset;
assign chnl_bus.tx_last = 1;
assign chnl_bus.tx_len = RC;
assign chnl_bus.tx_off = 0;
assign chnl_bus.tx_data_valid = acked;
// --------------------------------------------------------------------
//
endmodule
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