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[/] [qaz_libs/] [trunk/] [PCIe/] [syn/] [a10gx_riffa/] [a10gx_riffa.sdc] - Rev 49

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# ----------------------------------------------------------------------
# Copyright (c) 2016, The Regents of the University of California All
# rights reserved.
# 
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
# 
#     * Redistributions of source code must retain the above copyright
#       notice, this list of conditions and the following disclaimer.
# 
#     * Redistributions in binary form must reproduce the above
#       copyright notice, this list of conditions and the following
#       disclaimer in the documentation and/or other materials provided
#       with the distribution.
# 
#     * Neither the name of The Regents of the University of California
#       nor the names of its contributors may be used to endorse or
#       promote products derived from this software without specific
#       prior written permission.
# 
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
# DAMAGE.
# ----------------------------------------------------------------------
# ---------------------------------------------------------------------------
# Filename:            DE5QGen3x4If128.sdc (Qsys)
# Version:             1.00.a
# Verilog Standard:    Verilog-2001
# Description:         Synopsys Design Constraints for the DE5 board.
# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
# Author:              Dustin Richmond (@darichmond)
# ----------------------------------------------------------------------------
# create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]
# create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]

create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]
create_clock -name {clk_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk_50}]
# create_clock -name {pcie_ob_refclk_p} -period 10.000 [get_ports {pcie_ob_refclk_p}]
# create_clock -name {emif_0_pll_ref_clk_clk} -period 6.666 [ get_ports emif_0_pll_ref_clk_clk]

# derive_pll_clocks -create_base_clocks
# derive_clock_uncertainty

#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -clock altera_reserved_tck 6 [get_ports altera_reserved_tdi]
set_input_delay -clock altera_reserved_tck 6 [get_ports altera_reserved_tms]



#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -clock altera_reserved_tck -clock_fall -max 6 [get_ports altera_reserved_tdo]



#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]  
set_clock_groups -asynchronous -group [get_clocks { clk_50 }]  
# set_clock_groups -asynchronous -group [get_clocks { pcie_ob_refclk_p }] 
# set_clock_groups -asynchronous -group [get_clocks { emif_0_pll_ref_clk_clk }] 


#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from * -to [get_ports {user_led_g[*]}]
set_false_path -from * -to [get_ports {user_led_r[*]}]
set_false_path -from [get_ports {altera_reserved_ntrst}]
set_false_path -from [get_ports {cpu_resetn}]
# set_false_path -from [get_ports {emif_0_oct_oct_rzqin}]


#**************************************************************
# Set Multicycle Path
#**************************************************************



#**************************************************************
# Set Maximum Delay
#**************************************************************



#**************************************************************
# Set Minimum Delay
#**************************************************************



#**************************************************************
# Set Input Transition
#**************************************************************



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