Subversion Repositories qaz_libs

//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////


interface
  amm_slave_bfm_if
  #(
    A = 32, // address bus width
    N = 8   // data bus width in bytes
  )
  (
    amm_if amm_m,
    output reset,
    output clk
  );

        logic [(A-1):0]   address;
        logic             read;
        logic   [(8*N)-1:0] readdata;
        logic             write;
        logic   [(8*N)-1:0] writedata;
        logic   [N-1:0]     byteenable;
        logic             begintransfer;
        logic             waitrequest;
        logic             arbiterlock;
        logic             readdatavalid;
        logic   [6:0]       burstcount;
        logic               beginbursttransfer;
        logic               readyfordata;
        logic               dataavailable;
        logic               resetrequest;


  // --------------------------------------------------------------------
  //
  default clocking cb @(posedge clk);
    input   address;
    input   read;
    output  readdata;
    input   write;
    input   writedata;
    input   byteenable;
    input   begintransfer;
    output  waitrequest;
    input   arbiterlock;
    output  readdatavalid;
    input   burstcount;
    input   beginbursttransfer;
    output  readyfordata;
    output  dataavailable;
    output  resetrequest;
    input   reset;
    input   clk;
  endclocking


  // --------------------------------------------------------------------
  //
  assign address              = amm_m.address;
  assign read                 = amm_m.read;
  assign amm_m.readdata       = readdata;
  assign write                = amm_m.write;
  assign writedata            = amm_m.writedata;
  assign byteenable           = amm_m.byteenable;
  assign begintransfer        = amm_m.begintransfer;
  assign amm_m.waitrequest    = waitrequest;
  assign arbiterlock          = amm_m.arbiterlock;
  assign amm_m.readdatavalid  = readdatavalid;
  assign burstcount           = amm_m.burstcount;
  assign beginbursttransfer   = amm_m.beginbursttransfer;
  assign amm_m.readyfordata   = readyfordata;
  assign amm_m.dataavailable  = dataavailable;
  assign amm_m.resetrequest   = resetrequest;


  // --------------------------------------------------------------------
  //
  function void
    set_address_default;

    waitrequest   = 1;

  endfunction: set_address_default


  // --------------------------------------------------------------------
  //
  function void
    set_data_default;

    readdata      = 'bx;
    readdatavalid = 0;

  endfunction: set_data_default


  // --------------------------------------------------------------------
  //
  function void
    init;
    
    readyfordata  = 'bz;
    dataavailable = 'bz;
    resetrequest  = 'bz;

    set_address_default();
    set_data_default();

  endfunction: init


  // --------------------------------------------------------------------
  //
  task
    zero_cycle_delay;

    ##0;

  endtask: zero_cycle_delay


  // --------------------------------------------------------------------
  //
  import q_pkg::*;
  import axi4_transaction_pkg::*;


  // --------------------------------------------------------------------
  //
  class slave_write_transaction_class #(A = 32, N = 8, I = 1)
    extends blocking_transmission_q_class #(axi4_transaction_class);

    // --------------------------------------------------------------------
    //
    task automatic
      transmit
      (
        ref T tr_h
      );

      ->this.start;

      foreach(tr_h.payload_h.w[i])
      begin
        ##(tr_h.delay_h.next());

        cb.waitrequest <= 0;
        ##1;
        wait(cb.write);
        $display("^^^ %16.t | %m | AMM slave write  | %0d | 0x%016x |", $time, i, tr_h.payload_h.w[i]);
        cb.waitrequest <= 1;
      end

      set_address_default();
      set_data_default();

      ->this.done;

    endtask: transmit


  // --------------------------------------------------------------------
  //
  endclass: slave_write_transaction_class


  // --------------------------------------------------------------------
  //
  class slave_read_data_transaction_class #(A = 32, N = 8, I = 1)
    extends blocking_transmission_q_class #(axi4_transaction_class);

    // --------------------------------------------------------------------
    //
    task automatic
      transmit
      (
        ref T tr_h
      );

      ->this.start;

      foreach(tr_h.payload_h.w[i])
      begin
        if(tr_h.payload_h.w.size > 1)
          ##1;  // slave burst response must be at lease one cycle after read address phase

        ##(tr_h.delay_h.next());

        cb.readdata <= tr_h.payload_h.w[i];
        cb.readdatavalid <= 1;
        ##1;
        $display("^^^ %16.t | %m | AMM slave read data  | %0d of %0d | 0x%016x |", $time, i + 1, tr_h.payload_h.w.size, tr_h.payload_h.w[i]);
        cb.readdatavalid <= 0;
        cb.readdata <= 'bx;
      end

      set_data_default();

      ->this.done;

    endtask: transmit

  // --------------------------------------------------------------------
  //
  endclass: slave_read_data_transaction_class


  // --------------------------------------------------------------------
  //
  slave_read_data_transaction_class #(.A(A), .N(N), .I(1)) r_h;

  class slave_read_address_transaction_class #(A = 32, N = 8, I = 1)
    extends blocking_transmission_q_class #(axi4_transaction_class);

    // --------------------------------------------------------------------
    //
    task automatic
      transmit
      (
        ref T tr_h
      );

      ->this.start;

      ##(tr_h.delay_h.next());
      cb.waitrequest <= 0;
      ##1;

      wait(cb.read)
      ##0;
      $display("^^^ %16.t | %m | AMM slave read address | 0x%08x | %0d |", $time, tr_h.addr, tr_h.len + 1);

      r_h.put(tr_h);

      set_address_default();
      ->this.done;

    endtask: transmit


  // --------------------------------------------------------------------
  //
  endclass: slave_read_address_transaction_class


  // --------------------------------------------------------------------
  //
  slave_write_transaction_class #(.A(A), .N(N), .I(1)) w_h;
  slave_read_address_transaction_class #(.A(A), .N(N), .I(1)) ar_h;

  initial
  begin
    init();
    w_h = new;
    w_h.init();
    ar_h = new;
    ar_h.init();
    r_h = new;
    r_h.init();
  end


// --------------------------------------------------------------------
//

endinterface