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[/] [qaz_libs/] [trunk/] [avalon_lib/] [sim/] [tests/] [tb_ast_monitor/] [the_test.sv] - Rev 32

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
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//////////////////////////////////////////////////////////////////////

`timescale 1ps/1ps


module the_test(input tb_clk, input tb_rst);

  // --------------------------------------------------------------------
  //
  import verbosity_pkg::*;

     
  // --------------------------------------------------------------------
  //
  task run_the_test;

    // --------------------------------------------------------------------
    // insert test below
    // --------------------------------------------------------------------
    $display("^^^---------------------------------");
    $display("^^^ %16.t | Testbench begun.\n", $time);
    $display("^^^---------------------------------");
    // --------------------------------------------------------------------

    // --------------------------------------------------------------------
    tb_top.tb.timeout_stop(50us);
    
    // --------------------------------------------------------------------
    // set_verbosity(VERBOSITY_DEBUG);
    tb_top.ast_source_i.st_source_bfm_i.init();
    tb_top.ast_sink_i.st_sink_bfm_i.init();

    // --------------------------------------------------------------------
    wait(~tb_rst);

    // --------------------------------------------------------------------
    #200ns;
    tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(0);
    tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(1);
    tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(0);
    tb_top.ast_source_i.st_source_bfm_i.push_transaction();
    
    tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(1);
    tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(0);
    tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(0);
    tb_top.ast_source_i.st_source_bfm_i.push_transaction();
    
    tb_top.ast_source_i.st_source_bfm_i.set_transaction_data(2);
    tb_top.ast_source_i.st_source_bfm_i.set_transaction_sop(0);
    tb_top.ast_source_i.st_source_bfm_i.set_transaction_eop(1);
    tb_top.ast_source_i.st_source_bfm_i.push_transaction();
    

    // --------------------------------------------------------------------
    #200ns;
    @(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1);
    @(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0);
    @(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1);
    @(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0);
    @(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(1);
    @(posedge tb_clk) tb_top.ast_sink_i.st_sink_bfm_i.set_ready(0);


    // --------------------------------------------------------------------
    #1us;


    // --------------------------------------------------------------------
    // insert test above
    // --------------------------------------------------------------------

  endtask

// --------------------------------------------------------------------
//
endmodule

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