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[/] [qaz_libs/] [trunk/] [avalon_lib/] [src/] [amm_if.sv] - Rev 49
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
interface
amm_if
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
B = 7 // burstcount width
)
(
input reset,
input clk
);
logic [(A-1):0] address;
logic read;
logic [(8*N)-1:0] readdata;
logic write;
logic [(8*N)-1:0] writedata;
logic [N-1:0] byteenable;
logic begintransfer;
logic waitrequest;
logic arbiterlock;
logic readdatavalid;
logic [B-1:0] burstcount;
logic beginbursttransfer;
logic readyfordata;
logic dataavailable;
logic resetrequest;
logic chipselect;
// --------------------------------------------------------------------
//
endinterface
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