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[/] [qaz_libs/] [trunk/] [axi4_lib/] [src/] [axi4_if.sv] - Rev 29

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
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//////////////////////////////////////////////////////////////////////


interface
  axi4_if
  #(
    A = 32, // address bus width
    N = 8,  // data bus width in bytes
    I = 1   // ID width
  )
  (
    input           aresetn,
    input           aclk
  );

  logic [(A-1):0]    araddr;
  logic [1:0]        arburst;
  logic [3:0]        arcache;
  logic [(I-1):0]    arid;
  logic [7:0]        arlen;
  logic              arlock;
  logic [2:0]        arprot;
  logic [3:0]        arqos;
  logic              arready;
  logic [3:0]        arregion;
  logic [2:0]        arsize;
  logic              arvalid;
  logic [(A-1):0]    awaddr;
  logic [1:0]        awburst;
  logic [3:0]        awcache;
  logic [(I-1):0]    awid;
  logic [7:0]        awlen;
  logic              awlock;
  logic [2:0]        awprot;
  logic [3:0]        awqos;
  logic              awready;
  logic [3:0]        awregion;
  logic [2:0]        awsize;
  logic              awvalid;
  logic [(I-1):0]    bid;
  logic              bready;
  logic [1:0]        bresp;
  logic              bvalid;
  logic [(8*N)-1:0]  rdata;
  logic [(I-1):0]    rid;
  logic              rlast;
  logic              rready;
  logic [1:0]        rresp;
  logic              rvalid;
  logic [(8*N)-1:0]  wdata;
  logic [(I-1):0]    wid;
  logic              wlast;
  logic              wready;
  logic [N-1:0]      wstrb;
  logic              wvalid;


// --------------------------------------------------------------------
//

endinterface


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