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[/] [qaz_libs/] [trunk/] [axi4_lib/] [src/] [axi4_register_slice.sv] - Rev 29

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
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//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
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//////////////////////////////////////////////////////////////////////

module
  axi4_register_slice
  #(
    A = 32, // address bus width
    N = 8,  // data bus width in bytes
    I = 1,  // ID width
    USE_ADVANCED_PROTOCOL = 0
  )
  (
    axi4_if axi4_s,
    axi4_if axi4_m,
    input   aclk,
    input   aresetn
  );

  // --------------------------------------------------------------------
  //
  wire ar_rd_empty;
  wire ar_rd_en = axi4_m.arvalid & axi4_m.arready;
  wire r_wr_full;
  wire r_wr_en = axi4_m.rvalid & axi4_m.rready;

  axi4_if #(.A(A), .N(N), .I(I))
    axi4_read_fifo(.*);


  // --------------------------------------------------------------------
  //
  axi4_to_read_fifos
    #(
      .A(A),
      .N(N),
      .I(I),
      .USE_ADVANCED_PROTOCOL(USE_ADVANCED_PROTOCOL)
    )
    axi4_to_read_fifos_i(.*);


  // --------------------------------------------------------------------
  //
  assign axi4_m.arid    = axi4_read_fifo.arid;
  assign axi4_m.araddr  = axi4_read_fifo.araddr;
  assign axi4_m.arburst = axi4_read_fifo.arburst;
  assign axi4_m.arlen   = axi4_read_fifo.arlen;
  assign axi4_m.arsize  = axi4_read_fifo.arsize;
  assign axi4_m.arvalid = ~ar_rd_empty;

  generate
    begin: ar_assign_gen
      if(USE_ADVANCED_PROTOCOL)
      begin
        assign axi4_m.arcache   = axi4_read_fifo.arcache;
        assign axi4_m.arlock    = axi4_read_fifo.arlock;
        assign axi4_m.arprot    = axi4_read_fifo.arprot;
        assign axi4_m.arqos     = axi4_read_fifo.arqos;
        assign axi4_m.arregion  = axi4_read_fifo.arregion;
      end
      else
      begin
        assign axi4_m.arcache   = 0;
        assign axi4_m.arlock    = 0;
        assign axi4_m.arprot    = 0;
        assign axi4_m.arqos     = 0;
        assign axi4_m.arregion  = 0;
      end
    end
  endgenerate


  // --------------------------------------------------------------------
  //
  assign axi4_m.rready        = ~r_wr_full;
  assign axi4_read_fifo.rdata = axi4_m.rdata;
  assign axi4_read_fifo.rid   = axi4_m.rid;
  assign axi4_read_fifo.rlast = axi4_m.rlast;
  assign axi4_read_fifo.rresp = axi4_m.rresp;


  // --------------------------------------------------------------------
  //
  wire aw_rd_empty;
  wire aw_rd_en = axi4_m.awvalid & axi4_m.awready;
  wire w_rd_empty;
  wire w_rd_en = axi4_m.wvalid & axi4_m.wready;
  wire b_wr_full;
  wire b_wr_en = axi4_m.bvalid & axi4_m.bready;

  axi4_if #(.A(A), .N(N), .I(I))
    axi4_write_fifo(.*);


  // --------------------------------------------------------------------
  //
  axi4_to_write_fifos
    #(
      .A(A),
      .N(N),
      .I(I),
      .USE_ADVANCED_PROTOCOL(USE_ADVANCED_PROTOCOL)
    )
    axi4_to_write_fifos_i(.*);


  // --------------------------------------------------------------------
  //
  assign axi4_m.awid    = axi4_write_fifo.awid;
  assign axi4_m.awaddr  = axi4_write_fifo.awaddr;
  assign axi4_m.awburst = axi4_write_fifo.awburst;
  assign axi4_m.awlen   = axi4_write_fifo.awlen;
  assign axi4_m.awsize  = axi4_write_fifo.awsize;
  assign axi4_m.awvalid = ~aw_rd_empty;

  generate
    begin: aw_assign_gen
      if(USE_ADVANCED_PROTOCOL)
      begin
        assign axi4_m.awcache   = axi4_write_fifo.awcache;
        assign axi4_m.awlock    = axi4_write_fifo.awlock;
        assign axi4_m.awprot    = axi4_write_fifo.awprot;
        assign axi4_m.awqos     = axi4_write_fifo.awqos;
        assign axi4_m.awregion  = axi4_write_fifo.awregion;
      end
      else
      begin
        assign axi4_m.awcache   = 0;
        assign axi4_m.awlock    = 0;
        assign axi4_m.awprot    = 0;
        assign axi4_m.awqos     = 0;
        assign axi4_m.awregion  = 0;
      end
    end
  endgenerate


  // --------------------------------------------------------------------
  //
  assign axi4_m.wvalid  = ~w_rd_empty;
  assign axi4_m.wdata   = axi4_write_fifo.wdata;
  assign axi4_m.wid     = axi4_write_fifo.wid;
  assign axi4_m.wlast   = axi4_write_fifo.wlast;
  assign axi4_m.wstrb   = axi4_write_fifo.wstrb;


  // --------------------------------------------------------------------
  //
  assign axi4_m.bready        = ~b_wr_full;
  assign axi4_write_fifo.bid   = axi4_m.bid;
  assign axi4_write_fifo.bresp = axi4_m.bresp;


// --------------------------------------------------------------------
//

endmodule

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