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[/] [qaz_libs/] [trunk/] [axi4_lite_lib/] [src/] [axi4_lite_register_if.sv] - Rev 29

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//////////////////////////////////////////////////////////////////////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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//// This source file may be used and distributed without         ////
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////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
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//// later version.                                               ////
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//////////////////////////////////////////////////////////////////////


interface
  axi4_lite_register_if
  #(
    N   = 8,      //  data bus width in bytes, must be 4 or 8 for axi lite
    MW  = 3,      //  mux select width
    MI  = 2 ** MW //  mux inputs
  )
  (
    input aclk,
    input aresetn
  );

  wire  [(N*8)-1:0] register_in   [MI-1:0];
  reg   [(N*8)-1:0] register_out  [MI-1:0];


// --------------------------------------------------------------------
// synthesis translate_off
    initial
      a_data_bus_width: assert((N == 8) | (N == 4)) else $fatal;
// synthesis translate_on
// --------------------------------------------------------------------

// --------------------------------------------------------------------
//

endinterface


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