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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [sim/] [src/] [BP063-BU-01000-r0p1-00rel0/] [axis_checker.sv] - Rev 31

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////


module
  axis_checker
  #(
    N,      // data bus width in bytes
    I = 1,  // TID width
    D = 1,  // TDEST width
    U = 1,  // TUSER width
    MAXWAITS = 16,
    RecommendOn = 1'b1,
    RecMaxWaitOn = 1'b1
  )
  (
    axis_if axis_in
  );

  //---------------------------------------------------
  //
  localparam DATA_WIDTH_BYTES = N;         // data bus width
  localparam DEST_WIDTH = D;               // TDEST width

  // Select the number of ID bits required
  localparam ID_WIDTH = I;                 // (T)ID width

  // Select the size of the USER buses
  localparam USER_WIDTH  = U;            // width of the user sideband field


  //---------------------------------------------------
  //
  // INDEX:        - Calculated (user should not override)
  // =====
  // Do not override the following parameters: they must be calculated exactly
  // as shown below
  // data max index
  localparam    DATA_MAX = DATA_WIDTH_BYTES ? (DATA_WIDTH_BYTES*8)-1:0;
  localparam    DEST_MAX = DEST_WIDTH ? DEST_WIDTH-1:0;    // dest max index
  localparam  STRB_WIDTH = DATA_WIDTH_BYTES;               // TSTRB width
  localparam    STRB_MAX = STRB_WIDTH ? STRB_WIDTH-1:0;    // TSTRB max index
  localparam    KEEP_MAX = STRB_WIDTH ? STRB_WIDTH-1:0;    // TKEEP max index
  localparam      ID_MAX = ID_WIDTH ? ID_WIDTH-1:0;        // ID max index
  localparam   TUSER_MAX = USER_WIDTH? USER_WIDTH-1:0;   // TUSER  max index


  //---------------------------------------------------
  //
  // INDEX:        - Global Signals
  // =====
  wire                ACLK = axis_in.aclk;        // AXI Clock
  wire                ARESETn = axis_in.aresetn;     // AXI Reset


  // INDEX:        - AXI4-Stream Interface
  // =====
  wire   [DATA_MAX:0] TDATA = axis_in.tdata;
  wire   [STRB_MAX:0] TSTRB = axis_in.tstrb;
  wire   [KEEP_MAX:0] TKEEP = axis_in.tkeep;
  wire                TLAST = axis_in.tlast;
  wire     [ID_MAX:0] TID = axis_in.tid;
  wire   [DEST_MAX:0] TDEST = axis_in.tdest;
  wire  [TUSER_MAX:0] TUSER = axis_in.tuser;
  wire                TVALID = axis_in.tvalid;
  wire                TREADY = axis_in.tready;


  //---------------------------------------------------
  //
  Axi4StreamPC
    #(
                                             // Set DATA_WIDTH to the data-bus width required
      .DATA_WIDTH_BYTES(DATA_WIDTH_BYTES),   // data bus width
      .DEST_WIDTH(DEST_WIDTH),               // TDEST width

                                             // Select the number of ID bits required
      .ID_WIDTH(ID_WIDTH),                   // (T)ID width

                                             // Select the size of the USER buses
      .USER_WIDTH(USER_WIDTH),               // width of the user sideband field

                                             // Maximum number of cycles between VALID -> READY high before a warning is
                                             // generated
      .MAXWAITS(MAXWAITS),

                                             // Recommended Rules Enable
                                             // enable/disable reporting of all  AXI4STREAM_REC*_* rules
      .RecommendOn(RecommendOn),
                                             // enable/disable reporting of just AXI4STREAM_REC*_MAX_WAIT rules
      .RecMaxWaitOn(RecMaxWaitOn)
    )
    Axi4StreamPC_i(.*);


//---------------------------------------------------
//
endmodule

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