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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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//// This source file is free software; you can redistribute it   ////
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//////////////////////////////////////////////////////////////////////
// ----------------------------------------------------------------------------

import tb_axis_gear_box_pkg::*;
import tests_pkg::*;
import uvm_pkg::*;
`include "uvm_macros.svh"

module tb_top();

  // --------------------------------------------------------------------
  // test bench clock & reset
  wire clk_100mhz;
  wire tb_clk   = clk_100mhz;
  wire tb_rst;

  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);

  // --------------------------------------------------------------------
  //
  wire tb_rst_s;
  wire aclk     = tb_clk;
  wire aresetn  = ~tb_rst_s;
  wire clk      = tb_clk;
  wire reset    = tb_rst_s;

  sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);

  // --------------------------------------------------------------------
  //
  import tb_axis_gear_box_pkg::*;

  // --------------------------------------------------------------------
  //
  tb_dut_if #(dut_cfg) dut_bus(.*);

  // --------------------------------------------------------------------
  //
  axis_gear_box
    dut
    (
      .axis_in(dut_bus.axis_in),
      .axis_out(dut_bus.axis_out),
      .aclk(dut_bus.aclk),
      .aresetn(dut_bus.aresetn)
    );

  // --------------------------------------------------------------------
  //
  assign dut_bus.axis_out.tready = 1;
  
  // --------------------------------------------------------------------
  //
  tb_dut_config #(dut_cfg) cfg_h;

  initial
  begin
    cfg_h = new(dut_bus);
    uvm_config_db #(tb_dut_config #(dut_cfg))::set(null, "*env_h", "tb_dut_config", cfg_h);
    run_test("t_debug");
  end

// --------------------------------------------------------------------
//
endmodule