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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [sim/] [tests/] [legacy/] [tb_axis_gear_box/] [tb_axis_gear_box.sv] - Rev 50
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// ----------------------------------------------------------------------------
import tb_axis_gear_box_pkg::*;
import tests_pkg::*;
import uvm_pkg::*;
`include "uvm_macros.svh"
module tb_top();
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
// --------------------------------------------------------------------
//
wire tb_rst_s;
wire aclk = tb_clk;
wire aresetn = ~tb_rst_s;
wire clk = tb_clk;
wire reset = tb_rst_s;
sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);
// --------------------------------------------------------------------
//
import tb_axis_gear_box_pkg::*;
// --------------------------------------------------------------------
//
tb_dut_if #(dut_cfg) dut_bus(.*);
// --------------------------------------------------------------------
//
axis_gear_box
dut
(
.axis_in(dut_bus.axis_in),
.axis_out(dut_bus.axis_out),
.aclk(dut_bus.aclk),
.aresetn(dut_bus.aresetn)
);
// --------------------------------------------------------------------
//
assign dut_bus.axis_out.tready = 1;
// --------------------------------------------------------------------
//
tb_dut_config #(dut_cfg) cfg_h;
initial
begin
cfg_h = new(dut_bus);
uvm_config_db #(tb_dut_config #(dut_cfg))::set(null, "*env_h", "tb_dut_config", cfg_h);
run_test("t_debug");
end
// --------------------------------------------------------------------
//
endmodule