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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [sim/] [tests/] [tb_axis_to_axi4_basic_dma/] [tb_axis_to_axi4_basic_dma.sv] - Rev 31

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// --------------------------------------------------------------------
//
// --------------------------------------------------------------------


module tb_top();

  // --------------------------------------------------------------------
  // test bench clock & reset
  wire clk_200mhz;
  wire tb_clk   = clk_200mhz;
  wire tb_rst;

  tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);


  // --------------------------------------------------------------------
  //
  wire tb_rst_s;
  wire aclk     = tb_clk;
  wire aresetn  = ~tb_rst_s;

  sync_reset
    sync_reset_i(aclk, tb_rst, tb_rst_s);


  // --------------------------------------------------------------------
  //
  import tb_axis_to_axi4_basic_dma_pkg::*;


  // --------------------------------------------------------------------
  //
  axi4_if #(.A(A), .N(N), .I(I)) axi4_m(.*);
  axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*);


  // --------------------------------------------------------------------
  //
  logic dma_enable = 0;

  axis_to_axi4_basic_dma
    #(
      .A(A),
      .N(N),
      .I(I),
      .BASE_ADDRESS(BASE_ADDRESS),
      .BUFFER_SIZE(BUFFER_SIZE),
      .BURST_LENGTH(BURST_LENGTH),
      .MAX_BURSTS(MAX_BURSTS),
      .BYTES_PER_TUSER(BYTES_PER_TUSER)
    )
    dut(.*);


  // --------------------------------------------------------------------
  // sim models
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // --------------------------------------------------------------------
  //
  axi4_checker #(.A(A), .N(N), .MAXWAITS(64))
    axi4_checker_i(.axi4_in(axi4_m));


  // --------------------------------------------------------------------
  //
  axis_checker #(.N(N), .I(I), .D(D), .U(U), .MAXWAITS(64))
    axis_checker_i(.axis_in(axis_in));


  // --------------------------------------------------------------------
  //
  tb_axis_to_axi4_basic_dma_class a_h;

  initial
    a_h = new(axi4_m, axis_in);


  // --------------------------------------------------------------------
  //

  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // sim models
  // --------------------------------------------------------------------


  // --------------------------------------------------------------------
  //  debug wires


  // --------------------------------------------------------------------
  // test
  the_test test(tb_clk, tb_rst);

  initial
    begin

      test.run_the_test();

      $display("^^^---------------------------------");
      $display("^^^ %16.t | Testbench done.", $time);
      $display("^^^---------------------------------");

      $display("^^^---------------------------------");

      $stop();

    end

endmodule

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