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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_register_slice.sv] - Rev 28

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////

module
  axis_register_slice
  #(
    N = 8,          // data bus width in bytes
    I = 0,          // TID width
    D = 0,          // TDEST width
    U = 1,          // TUSER width
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
  )
  (
    input           axis_en,
    axis_if.slave   axis_in,
    axis_if.master  axis_out,
    input           aclk,
    input           aresetn
  );

  // --------------------------------------------------------------------
  //
  localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;

  fifo_write_if #(.W(W)) fifo_sink(aclk, ~aresetn);
  fifo_read_if  #(.W(W)) fifo_source(aclk, ~aresetn);

  tiny_sync_fifo #(.W(W))
    tiny_sync_fifo_i(.source(fifo_sink.fifo), .sink(fifo_source.fifo));


  // --------------------------------------------------------------------
  //
  wire data_to_axis_fsm_error;

  data_to_axis_fsm
    data_to_axis_fsm_i
    (
      .axis_tvalid(axis_out.tvalid),
      .axis_tready(axis_out.tready),
      .fifo_empty(fifo_source.empty),
      .fifo_rd_en(fifo_source.rd_en),
      .fifo_watermark(1'b1),
      .*
    );


  // --------------------------------------------------------------------
  //
  generate
    begin: assign_gen

      if(USE_TSTRB & USE_TKEEP)
      begin
        assign fifo_sink.wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tstrb,
            axis_in.tkeep
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tstrb,
            axis_out.tkeep
          } = fifo_source.rd_data;
      end
      else if(USE_TSTRB)
      begin
        assign fifo_sink.wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tstrb
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tstrb
          } = fifo_source.rd_data;
      end
      else if(USE_TKEEP)
      begin
        assign fifo_sink.wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tkeep
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tkeep
          } = fifo_source.rd_data;
      end
      else
      begin
        assign fifo_sink.wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser
          } = fifo_source.rd_data;
      end

    end
  endgenerate


  // --------------------------------------------------------------------
  //
  assign axis_in.tready   = ~fifo_sink.full;
  assign fifo_sink.wr_en  = axis_in.tvalid & ~fifo_sink.full;



endmodule

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