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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_synchronizer.sv] - Rev 38

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2016 Authors and OPENCORES.ORG                 ////
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//// This source file may be used and distributed without         ////
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//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
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//////////////////////////////////////////////////////////////////////

module
  axis_synchronizer
  #(
    N,              // data bus width in bytes
    I = 1,          // TID width
    D = 1,          // TDEST width
    U = 1,          // TUSER width
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0,  //  set to 1 to enable, 0 to disable
    FD
  )
  (
    axis_if axis_in,
    axis_if axis_out,
    input   aclk_in,
    input   aresetn_in,
    input   aclk_out,
    input   aresetn_out
  );

  // --------------------------------------------------------------------
  //
  localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;


  // --------------------------------------------------------------------
  //
  wire          wr_full;
  wire [W-1:0]  wr_data;
  wire          wr_en;

  wire          rd_empty;
  wire [W-1:0]  rd_data;
  wire          rd_en;

  defparam async_fifo_i.W=W; // why are these needed for recursive modules?
  defparam async_fifo_i.D=FD;
  async_fifo
  // async_fifo #(.W(W), .D(FD))
    async_fifo_i
    (
      .wr_clk(aclk_in),
      .wr_reset(~aresetn_in),
      .rd_clk(aclk_out),
      .rd_reset(~aresetn_out),
      .*
    );


  // --------------------------------------------------------------------
  //
  defparam axis_map_fifo_i.N=N; // why are these needed for recursive modules?
  defparam axis_map_fifo_i.I=I;
  defparam axis_map_fifo_i.D=D;
  defparam axis_map_fifo_i.U=U;
  defparam axis_map_fifo_i.USE_TSTRB=USE_TSTRB;
  defparam axis_map_fifo_i.USE_TKEEP=USE_TKEEP;
  defparam axis_map_fifo_i.W=W;
  axis_map_fifo
    // #(
      // .N(N),
      // .I(I),
      // .D(D),
      // .U(U),
      // .USE_TSTRB(USE_TSTRB),
      // .USE_TKEEP(USE_TKEEP),
      // .W(W)
    // )
    axis_map_fifo_i(.*);


  // --------------------------------------------------------------------
  //
  assign axis_in.tready   = ~wr_full;
  assign wr_en            = axis_in.tvalid & ~wr_full;
  assign axis_out.tvalid  = ~rd_empty;
  assign rd_en            = axis_out.tready & ~rd_empty;


// --------------------------------------------------------------------
//
endmodule

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