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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [data_to_axis_fsm.sv] - Rev 31

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////


module
  data_to_axis_fsm
  (
    input   axis_en,
    output  axis_tvalid,
    input   axis_tready,

    input   fifo_watermark,   // OK to use fifo_almost_full if FIFO is synchronous, assert to flush also 
    input   fifo_empty,
    output  fifo_rd_en,

    output  data_to_axis_fsm_error,

    input   aclk,
    input   aresetn
  );

  //---------------------------------------------------
  //  state machine binary definitions
  enum reg [3:0]  {
                      IDLE_STATE  = 4'b0001,
                      TVALID      = 4'b0010,
                      TREADY      = 4'b0100,
                      ERROR_STATE = 4'b1000
                    } state, next_state;


  //---------------------------------------------------
  //  state machine flop
  always_ff @(posedge aclk)
    if(~aresetn)
      state <= IDLE_STATE;
    else
      state <= next_state;


  //---------------------------------------------------
  //  state machine
  always_comb
    case(state)
      IDLE_STATE:   if(axis_en & fifo_watermark & ~fifo_empty)
                      if(axis_tready)
                        next_state <= TREADY;
                      else
                        next_state <= TVALID;
                    else
                      next_state <= IDLE_STATE;

      TVALID:       if(axis_tready)                 // wait for slave to be ready
                      next_state <= TREADY;
                    else
                      next_state <= TVALID;

      TREADY:       if(fifo_empty)                 // slave can accept data
                      next_state <= IDLE_STATE;
                    else if(axis_tready)
                      next_state <= TREADY;
                    else
                      next_state <= TVALID;

      ERROR_STATE:  next_state <= IDLE_STATE;

      default:      next_state <= ERROR_STATE;

    endcase


  //---------------------------------------------------
  //  outputs
  assign axis_tvalid            = (next_state == TVALID) | (next_state == TREADY);
  assign fifo_rd_en             = axis_tvalid & axis_tready;
  assign data_to_axis_fsm_error = (state == ERROR_STATE);


endmodule



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