OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [recursive_axis_catenate.sv] - Rev 38

Go to most recent revision | Compare with Previous | Blame | View Log

//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////


module
  recursive_axis_catenate
  #(
    N, // data bus width in bytes
    I = 1, // TID width
    D = 1, // TDEST width
    U = 1, // TUSER width
    U_IS_EOP = -1,
    MA, // mux select width
    MD = 2 ** MA
  )
  (
    axis_if         axis_in [MD-1:0],
    axis_if         axis_out,
    input           aclk,
    input           aresetn
  );

  // --------------------------------------------------------------------
  //
  generate
    if(MA == 1)
    begin: catenate_gen
      axis_catenate #(.N(N), .I(I), .D(D), .U(U), .U_IS_EOP(U_IS_EOP))
        axis_catenate_i(.*);
    end
    else
    begin: recursive_catenate_gen
      // --------------------------------------------------------------------
      //
      axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_catenate_out[1:0](.*);

      recursive_axis_catenate
        #(
          .N(N),
          .I(I),
          .D(D),
          .U(U),
          .U_IS_EOP(U_IS_EOP),
          .MA(MA - 1)
        )
        catenate_lo
        (
          .axis_in(axis_in[(MD/2)-1:0]),
          .axis_out(axis_catenate_out[0]),
          .*
        );

      // --------------------------------------------------------------------
      //
      recursive_axis_catenate
        #(
          .N(N),
          .I(I),
          .D(D),
          .U(U),
          .U_IS_EOP(U_IS_EOP),
          .MA(MA - 1)
        )
        catenate_hi
        (
          .axis_in(axis_in[MD-1:(MD/2)]),
          .axis_out(axis_catenate_out[1]),
          .*
        );

      // --------------------------------------------------------------------
      //
      axis_catenate
        #(
          .N(N),
          .I(I),
          .D(D),
          .U(U),
          .U_IS_EOP(U_IS_EOP)
        )
        axis_catenate_i(.axis_in(axis_catenate_out), .*);
    end
  endgenerate


// --------------------------------------------------------------------
//
endmodule

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.