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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
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//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
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//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
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//////////////////////////////////////////////////////////////////////


module tb_top();

  // --------------------------------------------------------------------
  // test bench clock & reset
  wire clk_200mhz;
  wire tb_clk   = clk_200mhz;
  wire tb_rst;
  wire aclk     = tb_clk;
  wire aresetn  = ~tb_rst;

  tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);
  
  wire clk_100mhz;
  tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz);

  
  // --------------------------------------------------------------------
  //
  localparam DSIZE = 8;
  localparam ASIZE = 4;
  
  wire [DSIZE-1:0]  rdata;
  wire              wfull;
  wire              rempty;
  wire [DSIZE-1:0]  wdata = 0;
  wire              winc = 0;
  wire              wclk = clk_100mhz;
  wire              wrst_n = ~tb_rst;
  wire              rinc = 0;
  wire              rclk = clk_200mhz;
  wire              rrst_n = ~tb_rst;

  fifo1 #(.DSIZE(8), .ASIZE(4)) 
    dut(.*);
    // (
      // output [DSIZE-1:0]  rdata,
      // output              wfull,
      // output              rempty,
      // input [DSIZE-1:0]   wdata,
      // input winc, wclk, wrst_n,
      // input rinc, rclk, rrst_n
    // );
  
  
  // --------------------------------------------------------------------
  // sim models
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // --------------------------------------------------------------------
  //


  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // sim models
  // --------------------------------------------------------------------


  // --------------------------------------------------------------------
  //  debug wires


  // --------------------------------------------------------------------
  // test
  the_test test( tb_clk, tb_rst );

  initial
    begin

      test.run_the_test();

      $display("^^^---------------------------------");
      $display("^^^ %16.t | Testbench done.", $time);
      $display("^^^---------------------------------");

      $display("^^^---------------------------------");

      $stop();

    end

endmodule