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[/] [qaz_libs/] [trunk/] [basal/] [sim/] [tests/] [tb_fifo/] [fifo_if.sv] - Rev 44

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////

interface
  fifo_if
  #(
    W,
    D,
    UB = $clog2(D)
  )
  (
    input reset,
    input clk
  );
  import uvm_pkg::*;
  `include "uvm_macros.svh"
  import tb_fifo_pkg::*;

  // --------------------------------------------------------------------
  wire          wr_full;
  wire  [W-1:0] wr_data;
  wire          wr_en;
  wire          rd_empty;
  wire  [W-1:0] rd_data;
  wire          rd_en;
  wire  [UB:0]  count;

  // --------------------------------------------------------------------
  default clocking cb @(posedge clk);
    input reset;
    input wr_full;
    input rd_empty;
    input rd_data;
    input count;
    inout rd_en;
    inout wr_en;
    inout wr_data;
  endclocking

  // --------------------------------------------------------------------
  task zero_cycle_delay;
    ##0;
  endtask: zero_cycle_delay

// --------------------------------------------------------------------
endinterface

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