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[/] [qaz_libs/] [trunk/] [basal/] [sim/] [tests/] [tb_fifo/] [tb_top.sv] - Rev 44

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////

module tb_top;
  import uvm_pkg::*;
  import tb_fifo_pkg::*;
  `include "uvm_macros.svh"

  // --------------------------------------------------------------------
  wire clk_100mhz;
  wire tb_clk = clk_100mhz;
  wire tb_rst;
  wire clk_1000mhz;

  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);

  // --------------------------------------------------------------------
  wire clk = clk_100mhz;
  wire reset = tb_rst;

  // --------------------------------------------------------------------
  fifo_if #(.W(W), .D(D)) dut_if(.*);

  sync_fifo #(.W(W), .D(D))
    dut
    (
      .wr_full(dut_if.wr_full),
      .wr_data(dut_if.wr_data),
      .wr_en(dut_if.wr_en),
      .rd_empty(dut_if.rd_empty),
      .rd_data(dut_if.rd_data),
      .rd_en(dut_if.rd_en),
      .count(dut_if.count),
      .clk(dut_if.clk),
      .reset(dut_if.reset)
    );


  // --------------------------------------------------------------------
  tb_dut_config #(.W(W), .D(D)) cfg_h = new(dut_if);

  initial
  begin
    uvm_config_db #(tb_dut_config #(.W(W), .D(D)))::set(null, "*", "tb_dut_config", cfg_h);
    run_test("t_debug");
  end

// --------------------------------------------------------------------
endmodule

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