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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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//////////////////////////////////////////////////////////////////////

`timescale 1ps/1ps


module tb_top();

  // --------------------------------------------------------------------
  // test bench clock & reset
  wire clk_200mhz;
  wire tb_clk   = clk_200mhz;
  wire tb_rst;

  tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);

  
  // --------------------------------------------------------------------
  //
  localparam A = 5;  // encoder select width
  localparam D = 2 ** A;
  
  
  // --------------------------------------------------------------------
  //
  reg [A-1:0] select = 0;
  wire [D-1:0] encoded;
  
  one_hot_encoder #(A)
    dut(.*);


  // --------------------------------------------------------------------
  // sim models
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

      

  // --------------------------------------------------------------------
  //

  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // sim models
  // --------------------------------------------------------------------


  // --------------------------------------------------------------------
  //  debug wires


  // --------------------------------------------------------------------
  // test
  initial
    begin

      // --------------------------------------------------------------------
      wait(~tb_rst)
      #50ns;
      
      repeat(D + 1)
        @(posedge tb_clk)
          select++;
      

      // --------------------------------------------------------------------
      #50ns;

      $display("^^^---------------------------------");
      $display("^^^ %16.t | Testbench done.", $time);
      $display("^^^---------------------------------");

      $display("^^^---------------------------------");

      $stop();

    end

endmodule