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[/] [qaz_libs/] [trunk/] [basal/] [src/] [FIFOs/] [tiny_async_fifo.sv] - Rev 34

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////


module
  tiny_async_fifo
  #(
    parameter W = 8
  )
  (
    output            wr_full,
    input  [W-1:0]    wr_data,
    input             wr_en,
    input             wr_clk,
    input             wr_reset,

    output            rd_empty,
    output  [W-1:0]   rd_data,
    input             rd_en,
    input             rd_clk,
    input             rd_reset
  );

  // --------------------------------------------------------------------
  //
  wire        writing = wr_en && ~wr_full;
  wire        reading = rd_en && ~rd_empty;


  // --------------------------------------------------------------------
  //
  function logic [1:0]
    grey_counter_2_bit
    (
      input logic [1:0] count
    );

      case(count)
        2'b00:  grey_counter_2_bit = 2'b00;
        2'b01:  grey_counter_2_bit = 2'b01;
        2'b10:  grey_counter_2_bit = 2'b11;
        2'b11:  grey_counter_2_bit = 2'b10;
      endcase

  endfunction


  // --------------------------------------------------------------------
  //  sync grey_wr_ptr to rd clk domain
  reg [1:0] grey_wr_ptr;
  reg [1:0] grey_wr_ptr_r;
  reg [1:0] grey_wr_ptr_s;

  always_ff @(posedge rd_clk)
    if(rd_reset)
      {grey_wr_ptr_s, grey_wr_ptr_r} <= 0;
    else
      {grey_wr_ptr_s, grey_wr_ptr_r} <= {grey_wr_ptr_r, grey_wr_ptr};


  // --------------------------------------------------------------------
  //  sync grey_rd_ptr to wr clk domain
  reg [1:0] grey_rd_ptr;
  reg [1:0] grey_rd_ptr_r;
  reg [1:0] grey_rd_ptr_s;

  always_ff @(posedge wr_clk)
    if(rd_reset)
      {grey_rd_ptr_s, grey_rd_ptr_r} <= 0;
    else
      {grey_rd_ptr_s, grey_rd_ptr_r} <= {grey_rd_ptr_r, grey_rd_ptr};


  // --------------------------------------------------------------------
  //
  reg [1:0]   bin_rd_ptr;
  wire [1:0]  bin_rd_ptr_next = bin_rd_ptr + reading;

  always_ff @(posedge rd_clk)
    if(rd_reset)
      bin_rd_ptr <= 0;
    else
      bin_rd_ptr <= bin_rd_ptr_next;


  // --------------------------------------------------------------------
  //
  wire [1:0] grey_rd_ptr_next = grey_counter_2_bit(bin_rd_ptr_next);

  always_ff @(posedge rd_clk)
    if(rd_reset)
      grey_rd_ptr <= 0;
    else
      grey_rd_ptr <= grey_rd_ptr_next;


  // --------------------------------------------------------------------
  //
  reg asf_empty_r;

  always_ff @(posedge rd_clk)
    if(rd_reset)
      asf_empty_r <= 1;
    else
      asf_empty_r <= (grey_rd_ptr_next == grey_wr_ptr_s);


  // --------------------------------------------------------------------
  //
  reg [1:0] bin_wr_ptr;
  wire [1:0] bin_wr_ptr_next = bin_wr_ptr + writing;

  always_ff @(posedge wr_clk)
    if(wr_reset)
      bin_wr_ptr <= 0;
    else
      bin_wr_ptr <= bin_wr_ptr_next;


  // --------------------------------------------------------------------
  //
  wire [1:0] grey_wr_ptr_next = grey_counter_2_bit(bin_wr_ptr_next);

  always_ff @(posedge wr_clk)
    if(wr_reset)
      grey_wr_ptr <= 0;
    else
      grey_wr_ptr <= grey_wr_ptr_next;


  // --------------------------------------------------------------------
  //
  reg asf_full_r;

  always_ff @(posedge wr_clk)
    if(wr_reset)
      asf_full_r <= 1;
    else
      asf_full_r <= (grey_wr_ptr_next == ~grey_rd_ptr_s);


  // --------------------------------------------------------------------
  //
  reg   [W-1:0] data_0_r;
  reg   [W-1:0] data_1_r;
  wire  [W-1:0] rd_data_mux = bin_rd_ptr[0] ? data_1_r : data_0_r;
  assign rd_data = rd_data_mux;

  always_ff @(posedge wr_clk)
    if (writing)
      if(bin_wr_ptr[0])
        data_1_r <= wr_data;
      else
        data_0_r <= wr_data;


  // --------------------------------------------------------------------
  //
  assign rd_empty   = asf_empty_r;
  assign wr_full  = asf_full_r;


endmodule


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