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//////////////////////////////////////////////////////////////////////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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module
  recursive_mux
  #(
    A,  // mux select width
    W, // data width
    D = 2 ** A
  )
  (
    input   [A-1:0] select,
    input   [W-1:0] data_in [D-1:0],
    output  [W-1:0] data_out
  );

  // --------------------------------------------------------------------
  //
  generate
    if(A == 1)
    begin: mux_gen
        assign data_out = select ? data_in[1] : data_in[0];
    end
    else
    begin: recurse_mux_gen
      wire [W-1:0] data_out_lo, data_out_hi;

      recursive_mux #(.A(A - 1), .W(W))
        mux_lo
        (
          .select(select[A-2:0]),
          .data_in(data_in[(D/2)-1:0]),
          .data_out(data_out_lo)
        );

      recursive_mux #(.A(A - 1), .W(W))
        mux_hi
        (
          .select(select[A-2:0]),
          .data_in(data_in[D-1:(D/2)]),
          .data_out(data_out_hi)
        );

      assign data_out = select[A-1] ? data_out_hi : data_out_lo;
    end
  endgenerate



// --------------------------------------------------------------------
//

endmodule

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