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[/] [qaz_libs/] [trunk/] [basal/] [src/] [synchronize/] [pulse_synchronizer.v] - Rev 37

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//////////////////////////////////////////////////////////////////////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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//// This source file may be used and distributed without         ////
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//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
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//// later version.                                               ////
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//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
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//////////////////////////////////////////////////////////////////////
 
 
module
  pulse_synchronizer
  (
    input   in,
    output  out,
    output  busy,
 
    input   in_clk,
    input   in_reset,
    input   out_clk,
    input   out_reset
  );
 
 
  // --------------------------------------------------------------------
  //
  reg [1:0] in_s;
  reg in_r;
  wire in_w = in ? 1 : (in_s[1] ? 0 : in_r);
 
  always @(posedge in_clk)
    if(in_reset)
      in_r <= 0;
    else
      in_r <= in_w;
 
 
  // --------------------------------------------------------------------
  //
  reg [2:0] out_r;
 
  always @(posedge out_clk)
    if(out_reset)
      out_r <= 0;
    else
      out_r <= {out_r[1:0], in_r};
 
 
  // --------------------------------------------------------------------
  //  
  always @(posedge in_clk)
    if(in_reset)
      in_s <= 0;
    else
      in_s <= {in_s[0], out_r[1]};
 
 
  // --------------------------------------------------------------------
  //
  assign out = out_r[1] & ~out_r[2];
  assign busy = in_s[1] | in_r;
 
 
// --------------------------------------------------------------------
//
endmodule
 
 

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