OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [zed_board/] [syn/] [axi_lite_to_wb/] [axi_lite_to_wb.xpr] - Rev 27

Compare with Previous | Blame | View Log

<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2016.2 (64-bit)              -->
<!--                                                         -->
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.   -->

<Project Version="7" Minor="14" Path="C:/qaz/projects/qaz_libs/zed_board/syn/axi_lite_to_wb/axi_lite_to_wb.xpr">
  <DefaultLaunch Dir="$PRUNDIR"/>
  <Configuration>
    <Option Name="Id" Val="432ec04279194c02b84aac8f9ba987fe"/>
    <Option Name="Part" Val="xc7z020clg484-1"/>
    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
    <Option Name="CompiledLibDirXSim" Val=""/>
    <Option Name="CompiledLibDirModelSim" Val="C:/qaz/projects/qaz_libs/zed_board/syn/axi_lite_to_wb/axi_lite_to_wb.cache/compile_simlib/modelsim"/>
    <Option Name="CompiledLibDirQuesta" Val="C:/qaz/projects/qaz_libs/zed_board/syn/axi_lite_to_wb/axi_lite_to_wb.cache/compile_simlib/questa"/>
    <Option Name="CompiledLibDirIES" Val="C:/qaz/projects/qaz_libs/zed_board/syn/axi_lite_to_wb/axi_lite_to_wb.cache/compile_simlib/ies"/>
    <Option Name="CompiledLibDirVCS" Val="C:/qaz/projects/qaz_libs/zed_board/syn/axi_lite_to_wb/axi_lite_to_wb.cache/compile_simlib/vcs"/>
    <Option Name="CompiledLibDirRiviera" Val="C:/qaz/projects/qaz_libs/zed_board/syn/axi_lite_to_wb/axi_lite_to_wb.cache/compile_simlib/riviera"/>
    <Option Name="CompiledLibDirActivehdl" Val="C:/qaz/projects/qaz_libs/zed_board/syn/axi_lite_to_wb/axi_lite_to_wb.cache/compile_simlib/activehdl"/>
    <Option Name="BoardPart" Val="em.avnet.com:zed:part0:1.2"/>
    <Option Name="ActiveSimSet" Val="sim_1"/>
    <Option Name="DefaultLib" Val="xil_defaultlib"/>
    <Option Name="EnableCoreContainer" Val="FALSE"/>
    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
    <Option Name="IPUserFilesDir" Val="$PPRDIR/axi_lite_to_wb.ip_user_files"/>
    <Option Name="IPStaticSourceDir" Val="$PPRDIR/axi_lite_to_wb.ip_user_files/ipstatic"/>
    <Option Name="EnableBDX" Val="FALSE"/>
    <Option Name="DSABoardId" Val="zed"/>
    <Option Name="WTXSimLaunchSim" Val="0"/>
    <Option Name="WTModelSimLaunchSim" Val="0"/>
    <Option Name="WTQuestaLaunchSim" Val="0"/>
    <Option Name="WTIesLaunchSim" Val="0"/>
    <Option Name="WTVcsLaunchSim" Val="0"/>
    <Option Name="WTRivieraLaunchSim" Val="0"/>
    <Option Name="WTActivehdlLaunchSim" Val="0"/>
    <Option Name="WTXSimExportSim" Val="0"/>
    <Option Name="WTModelSimExportSim" Val="0"/>
    <Option Name="WTQuestaExportSim" Val="0"/>
    <Option Name="WTIesExportSim" Val="0"/>
    <Option Name="WTVcsExportSim" Val="0"/>
    <Option Name="WTRivieraExportSim" Val="0"/>
    <Option Name="WTActivehdlExportSim" Val="0"/>
  </Configuration>
  <FileSets Version="1" Minor="31">
    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
      <Filter Type="Srcs"/>
      <File Path="$PPRDIR/../../src/reg_file_v1_0_S00_AXI.v">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PSRCDIR/sources_1/bd/zync/zync.bd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
        <CompFileExtendedInfo CompFileName="zync.bd" FileRelPathName="zync_ooc.xdc"/>
        <CompFileExtendedInfo CompFileName="zync.bd" FileRelPathName="hdl/zync.v"/>
        <CompFileExtendedInfo CompFileName="zync.bd" FileRelPathName="ip/zync_processing_system7_0_0/zync_processing_system7_0_0.xci"/>
        <CompFileExtendedInfo CompFileName="zync.bd" FileRelPathName="ip/zync_axi_interconnect_0_0/zync_axi_interconnect_0_0.xci"/>
        <CompFileExtendedInfo CompFileName="zync.bd" FileRelPathName="ip/zync_proc_sys_reset_0_0/zync_proc_sys_reset_0_0.xci"/>
        <CompFileExtendedInfo CompFileName="zync.bd" FileRelPathName="ip/zync_auto_pc_0/zync_auto_pc_0.xci"/>
        <CompFileExtendedInfo CompFileName="zync.bd" FileRelPathName="hdl/zync.hwdef"/>
        <CompFileExtendedInfo CompFileName="zync.bd" FileRelPathName="hw_handoff/zync_bd.tcl"/>
        <CompFileExtendedInfo CompFileName="zync.bd" FileRelPathName="hw_handoff/zync.hwh"/>
      </File>
      <File Path="$PPRDIR/../../src/top.v">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <Config>
        <Option Name="DesignMode" Val="RTL"/>
        <Option Name="TopModule" Val="top"/>
      </Config>
    </FileSet>
    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
      <Filter Type="Constrs"/>
      <File Path="$PPRDIR/../../src/zedboard_master_XDC_RevC_D_v2.xdc">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
        </FileInfo>
      </File>
      <Config>
        <Option Name="TargetConstrsFile" Val="$PPRDIR/../../src/zedboard_master_XDC_RevC_D_v2.xdc"/>
        <Option Name="ConstrsType" Val="XDC"/>
      </Config>
    </FileSet>
    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
      <Filter Type="Srcs"/>
      <Config>
        <Option Name="DesignMode" Val="RTL"/>
        <Option Name="TopModule" Val="top"/>
        <Option Name="TransportPathDelay" Val="0"/>
        <Option Name="TransportIntDelay" Val="0"/>
        <Option Name="SrcSet" Val="sources_1"/>
      </Config>
    </FileSet>
  </FileSets>
  <Simulators>
    <Simulator Name="XSim">
      <Option Name="Description" Val="Vivado Simulator"/>
      <Option Name="CompiledLib" Val="0"/>
    </Simulator>
    <Simulator Name="ModelSim">
      <Option Name="Description" Val="ModelSim Simulator"/>
    </Simulator>
    <Simulator Name="Questa">
      <Option Name="Description" Val="Questa Advanced Simulator"/>
    </Simulator>
    <Simulator Name="IES">
      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
    </Simulator>
    <Simulator Name="VCS">
      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
    </Simulator>
    <Simulator Name="Riviera">
      <Option Name="Description" Val="Riviera-PRO Simulator"/>
    </Simulator>
    <Simulator Name="ActiveHDL">
      <Option Name="Description" Val="Active-HDL Simulator"/>
    </Simulator>
  </Simulators>
  <Runs Version="1" Minor="10">
    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
        <Step Id="synth_design"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
    </Run>
    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
        <Step Id="init_design"/>
        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>
        <Step Id="place_design"/>
        <Step Id="post_place_power_opt_design"/>
        <Step Id="phys_opt_design"/>
        <Step Id="route_design"/>
        <Step Id="post_route_phys_opt_design"/>
        <Step Id="write_bitstream"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
    </Run>
  </Runs>
</Project>

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.