Subversion Repositories reed_solomon_coder

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: University of Hamburg, University of Kiel, Germany
// Engineer: Cagil Gümüs, Andreas Bahr
// 
// Create Date:    17:47:25 01/18/2016 
// Design Name: 
// Module Name:    top_module_RS 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module top_module_RS(
 
	input wire 				clk,
	input wire 				reset,
	input wire [35:0]		data_in,	
	input wire 				global_start,
	input wire 				corrector_ready,
 
	output wire 			error,
	output wire [3:0] 	errorlocation_1,
	output wire [3:0]		errorlocation_2,
	output wire [3:0]		errormagnitude_1,
	output wire [3:0]		errormagnitude_2,
	output reg 				global_ready,
	output reg 				decoding,
	output reg 	[15:0]	number_of_errors,
	output reg 	[15:0]	number_of_errors2,
	output reg 	[15:0]	number_of_packets,
	output reg 	[15:0]	number_of_packets2
    );
 
 
 
reg	go_BM_reg;  		//Used to give go signal to BerlekampMassey block
reg 	go_chien_reg;		//Used to give go signal to Chien Search block
reg	go_forney_reg;		//Used to give go signal to Forney block
reg 	go_syndrome_reg;
 
reg job_done_reg;
 
 
wire 	ready_BM_wire;		//Used to get the ready signal from BerlekampMassey block
wire	ready_chien_wire;	//Used to get the ready signal from Chien block
wire	ready_forney_wire;//Used to get the ready signal from Forney block
wire 	ready_syndrome_wire;
 
wire [3:0] errorlocation_1_wire;
wire [3:0] errorlocation_2_wire;
wire [3:0] errormagnitude_1_wire;
wire [3:0] errormagnitude_2_wire;
 
wire no_errors_wire;
 
assign error = ~no_errors_wire;
 
	Middle middle1(
 
	.clk(clk),
	.reset(reset),
	.data_in(data_in),
 
	.go_BM(go_BM_reg),
	.go_chien(go_chien_reg),
	.go_forney(go_forney_reg),
	.go_syndrome(go_syndrome_reg),
 
	.ready_BM(ready_BM_wire),
	.ready_chien(ready_chien_wire),
	.ready_forney(ready_forney_wire),
	.ready_syndrome(ready_syndrome_wire),
 
	.errorlocation1(errorlocation_1),
	.errorlocation2(errorlocation_2),
 
	.errormagnitude1(errormagnitude_1),
	.errormagnitude2(errormagnitude_2),
 
	.no_errors(no_errors_wire),
 
	.job_done(job_done_reg),
	.errorlocator()
 
	);
 
 
 
//Finite State Machine Initialization
reg [3:0] state;
 
parameter [3:0] IDLE 					= 4'b0000,
					 SYNDROME				= 4'b1111,
					 BERLEKAMP				= 4'b0001,	
					 CHIEN					= 4'b0010,
					 FORNEY					= 4'b0011,
					 CORRECTOR				= 4'b0101,
					 FINISH					= 4'b0111 ;
 
 
//Main Block
always @(posedge clk or negedge reset)
 
	begin
 
		if(!reset)
			begin
 
 
 
				state <= IDLE; 
 
				job_done_reg <= 0;
				decoding 			<= 0;
				global_ready 		<= 0;
 
				go_BM_reg 			<= 0;
				go_chien_reg 		<= 0;
				go_forney_reg 		<= 0;
				go_syndrome_reg   <= 0; 
 
 
				number_of_errors 	<= 0;
				number_of_errors2 <= 0;
 
				number_of_packets <= 0;
				number_of_packets2<= 0;
 
			end
 
		else
			begin
 
				case(state)
 
					IDLE:
						begin
 
 
 
							global_ready <= 0;
 
							decoding			<= 0;
 
							go_BM_reg	 	<= 0;		
							go_chien_reg 	<= 0;
							go_forney_reg 	<= 0;
 
							if(global_start)
								begin
									job_done_reg <= 0;
									state <= SYNDROME;
 
								end
							else
								begin
									state <= IDLE;
									job_done_reg <= 1;
								end
						end
 
 
					SYNDROME:
							begin
 
 
									go_syndrome_reg 	<= 1;
									go_BM_reg		 	<= 0;		
									go_chien_reg 		<= 0;
									go_forney_reg 		<= 0;
 
									if(ready_syndrome_wire)
										begin
											if(no_errors_wire)
												begin
 
													state <= CORRECTOR;		//If all syndromes are zero skip to end state "FINISH" since there is no errors to compute.
 
													number_of_packets <= number_of_packets + 1; 
													if(number_of_packets == 16'b1111_1111_1111_1111)
														number_of_packets2 <= number_of_packets2 + 1 ;
 
												end
											else
												begin
													state <= BERLEKAMP;
 
													number_of_packets <= number_of_packets + 1; 
													if(number_of_packets == 16'b1111_1111_1111_1111)
														number_of_packets2 <= number_of_packets2 + 1 ;
 
													number_of_errors <= number_of_errors + 1; 
													if(number_of_errors == 16'b1111_1111_1111_1111)
														number_of_errors2 <= number_of_errors2 + 1 ;
 
												end
										end
									else
										state <= SYNDROME; 
 
 
 
							end 
 
 
					BERLEKAMP:
							begin
 
 
 
								decoding <= 1;
 
								go_syndrome_reg 	<= 0;
								go_BM_reg		 	<= 1;		
								go_chien_reg 		<= 0;
								go_forney_reg 		<= 0;
 
								if(ready_BM_wire)
									state <= CHIEN;
								else
									state <= BERLEKAMP;
 
 
							end
 
					CHIEN:
							begin
 
 
								go_syndrome_reg 	<= 0;
								go_BM_reg		 	<= 0;		
								go_chien_reg 		<= 1;
								go_forney_reg 		<= 0;
 
								if(ready_chien_wire)
									state <= FORNEY;
								else
									state <= CHIEN;
 
							end
 
					FORNEY:
							begin
 
 
 
									go_syndrome_reg 	<= 0;
									go_BM_reg		 	<= 0;		
									go_chien_reg 		<= 0;
									go_forney_reg 		<= 1;
 
								if(ready_forney_wire)
									state <= CORRECTOR;
								else
									state <= FORNEY;
 
 
							end
 
					CORRECTOR:
							begin
 
 
								go_syndrome_reg <= 0;								
								go_BM_reg <= 0;		
								go_chien_reg <= 0;
								go_forney_reg <= 0;
 
								global_ready <= 1;
 
 
								if(corrector_ready)
									state <= FINISH;
								else
									state <= CORRECTOR;
 
							end
 
					FINISH:
							begin
 
 
								job_done_reg <= 1;
								state <= IDLE;
 
							end
 
					default: state <= IDLE;
 
 
 
				endcase
 
 
 
 
 
 
			end
 
 
	end
 
 
 
endmodule