Subversion Repositories reed_solomon_coder

`timescale 1 ns / 1 ps
///////////////////////////////////////////////////////////////////////////////////
// Company: University of Hamburg, University of Kiel, Germany
// Engineer: Bibin John, Cagil Gümüs, Andreas Bahr
// 
// Create Date:    14:29:45 12/11/2015 
// Design Name: 
// Module Name:    RS_encoder 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: Reed Solomon encoder for 4 bit data
// n=9, k=5, 2t=4, 4bits/symbol
// primitive polynomial p(x)=x^4+x+1
// generator polynomial g(x)=x^4+13x^3+12x^2+8x+7
// Dependencies:
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
 
module reedSolomon(din, clkinp, reset, enable, valid, dout);
 
input clkinp, reset, enable;
input [19:0] din;
output valid;
output [15:0] dout;
 
//output [3:0] z0, z1, z2, z3;
 
reg [15:0] dout;
reg valid;
reg[3:0] counter;
 
//reg [3:0]datainp; //data input to RS encoder
 
wire [3:0] m0, m1, m2, m3;
//wire [3:0] z0, z1, z2, z3;
reg [3:0] q0, q1, q2, q3;
reg [3:0] fback;
 
always @(posedge clkinp or negedge reset)
begin
	if(~reset) 
	begin
		dout <= 0; 
		valid <=0;
		counter<=0;
		q0 <= 0; q1 <= 0; q2 <= 0; q3 <= 0;
		fback <= 0;
	end
	else
	begin
		if(enable==0)
		begin
			valid <=0;
			counter<=0;
			q0 <= 0; q1 <= 0; q2 <= 0; q3 <= 0;
			fback <= 0;
		end
		else
		begin if (~valid)
		   begin
			counter<=counter+1;
			case(counter)
				4'b0001 : 
					begin
						fback <= q3 ^ din[19:16];
					end
				4'b0010 : 
					begin
						q0 <= m0;
						q1 <= m1 ^ q0;
						q2 <= m2 ^ q1;
						q3 <= m3 ^ q2;
					end
				4'b0011 : 
					begin
						fback <= q3 ^ din[15:12];
					end
				4'b0100 : 
					begin
						q0 <= m0;
						q1 <= m1 ^ q0;
						q2 <= m2 ^ q1;
						q3 <= m3 ^ q2;
					end
				4'b0101 : 
					begin
						fback <= q3 ^ din[11:8];
					end
				4'b0110 : 
					begin
						q0 <= m0;
						q1 <= m1 ^ q0;
						q2 <= m2 ^ q1;
						q3 <= m3 ^ q2;
					end
				4'b0111 : 
					begin
						fback <= q3 ^ din[7:4];
					end
				4'b1000 : 
					begin
						q0 <= m0;
						q1 <= m1 ^ q0;
						q2 <= m2 ^ q1;
						q3 <= m3 ^ q2;
					end
				4'b1001 : 
					begin
						fback <= q3 ^ din[3:0];
					end
				4'b1010 : 
					begin
						q0 <= m0;
						q1 <= m1 ^ q0;
						q2 <= m2 ^ q1;
						q3 <= m3 ^ q2;
					end
				4'b1011 : 
					begin
						dout<={q3,q2,q1,q0};
						valid <= 1;
					end
				default :
					begin
						q0 <= 0; q1 <= 0; q2 <= 0; q3 <= 0;
						fback <= 0;
					end
			endcase
		   end
		   else
			begin
				q0 <= 0; q1 <= 0; q2 <= 0; q3 <= 0;
				fback <= 0;
			end
		end	
	end	
end
 
//coefficients for the generator polynomial
//x^4+13x^3+12x^2+8x+7
parameter [3:0] gin0=4'd7, gin1=4'd8, gin2=4'd12, gin3=4'd13; 
 
GFMULT u0(clkinp, reset, enable, fback, gin0, m0);
GFMULT u1(clkinp, reset, enable, fback, gin1, m1);
GFMULT u2(clkinp, reset, enable, fback, gin2, m2);
GFMULT u3(clkinp, reset, enable, fback, gin3, m3);
endmodule 
 
module GFMULT(clk, reset, enable, a, gin, z);
//lookup tables for  multiplication
 
//4'd7=alpha^10(x^2+x+1)
parameter [63:0] mult_gin0 ={4'd0,4'd7,4'd14,4'd9,4'd15,4'd8,4'd1,4'd6,4'd13,4'd10,4'd3,4'd4,4'd2,4'd5,4'd12,4'd11};
 //parameter [63:0] mult_gin0 ={0,7,14,9,15,8,1,6,13,10,3,4,2,5,12,11};
 
//mult_gin0[0]=4'b1111;
//4'd8=alpha^3(x^3)
parameter [63:0] mult_gin1={4'd0,4'd8,4'd3,4'd11,4'd6,4'd14,4'd5,4'd13,4'd12,4'd4,4'd15,4'd7,4'd10,4'd2,4'd9,4'd1}; 
 // parameter [63:0] mult_gin1={0,8,3,11,6,14,5,13,12,4,15,7,10,2,9,1};
 
//4'd12=alpha^6(x^3+x^2)
parameter [63:0] mult_gin2={4'd0,4'd12,4'd11,4'd7,4'd5,4'd9,4'd14,4'd2,4'd10,4'd6,4'd1,4'd13,4'd15,4'd3,4'd4,4'd8};
 // parameter [63:0] mult_gin2={0,12,11,7,5,9,14,2,10,6,1,13,15,3,4,8};
 
//4'd13=alpha^13(x^3+x^2+1)
parameter [63:0] mult_gin3= {4'd0,4'd13,4'd9,4'd4,4'd1,4'd12,4'd8,4'd5,4'd2,4'd15,4'd11,4'd6,4'd3,4'd14,4'd10,4'd7};
// parameter [63:0] mult_gin3= {0,13,9,4,1,12,8,5,2,15,11,6,3,14,10,7};
input clk, reset, enable;
input [3:0] a;
input [3:0] gin;
reg [5:0] ginp;
output [3:0] z;
reg [3:0] z;
always @(negedge clk or negedge reset)
begin
	if(~reset) 
	begin
		z <= 4'b0000; 
	end
	else
	begin 
		if(enable==0)
		begin
			z <= 4'b0000; 
		end
		else
		begin
			if (gin==4'd7)
			begin
			case(a)	
			1:begin z<=mult_gin0[59:56]; end
			2:begin z<=mult_gin0[55:52]; end
			3:begin z<=mult_gin0[51:48]; end
			4:begin z<=mult_gin0[47:44];end
			5:begin z<=mult_gin0[43:40];end
			6:begin z<=mult_gin0[39:36];end
			7:begin z<=mult_gin0[35:32];end
			8:begin z<=mult_gin0[31:28];end
			9:begin z<=mult_gin0[27:24];end
			10:begin z<=mult_gin0[23:20];end
			11:begin z<=mult_gin0[19:16];end
			12:begin z<=mult_gin0[15:12];end
			13:begin z<=mult_gin0[11:8];end
			14:begin z<=mult_gin0[7:4];end
			15:begin z<=mult_gin0[3:0];end
			default: begin z<=mult_gin0[63:60];end
			endcase	
			end
 
			else if(gin==4'd8)
			begin
			case(a)	
				1:begin z<=mult_gin1[59:56]; end
				2:begin z<=mult_gin1[55:52]; end
				3:begin z<=mult_gin1[51:48]; end
				4:begin z<=mult_gin1[47:44];end
				5:begin z<=mult_gin1[43:40];end
				6:begin z<=mult_gin1[39:36];end
				7:begin z<=mult_gin1[35:32];end
				8:begin z<=mult_gin1[31:28];end
				9:begin z<=mult_gin1[27:24];end
				10:begin z<=mult_gin1[23:20];end
				11:begin z<=mult_gin1[19:16];end
				12:begin z<=mult_gin1[15:12];end
				13:begin z<=mult_gin1[11:8];end
				14:begin z<=mult_gin1[7:4];end
				15:begin z<=mult_gin1[3:0];end
				default: begin z<=mult_gin1[63:60];end
			endcase
			end
 
			else if(gin==4'd12)
			begin
			case(a)	
				1:begin z<=mult_gin2[59:56]; end
				2:begin z<=mult_gin2[55:52]; end
				3:begin z<=mult_gin2[51:48]; end
				4:begin z<=mult_gin2[47:44];end
				5:begin z<=mult_gin2[43:40];end
				6:begin z<=mult_gin2[39:36];end
				7:begin z<=mult_gin2[35:32];end
				8:begin z<=mult_gin2[31:28];end
				9:begin z<=mult_gin2[27:24];end
				10:begin z<=mult_gin2[23:20];end
				11:begin z<=mult_gin2[19:16];end
				12:begin z<=mult_gin2[15:12];end
				13:begin z<=mult_gin2[11:8];end
				14:begin z<=mult_gin2[7:4];end
				15:begin z<=mult_gin2[3:0];end
				default: begin z<=mult_gin2[63:60];end
				endcase
			end
 
			else if(gin==4'd13)
			begin
			case(a)	
				1:begin z<=mult_gin3[59:56]; end
				2:begin z<=mult_gin3[55:52]; end
				3:begin z<=mult_gin3[51:48]; end
				4:begin z<=mult_gin3[47:44];end
				5:begin z<=mult_gin3[43:40];end
				6:begin z<=mult_gin3[39:36];end
				7:begin z<=mult_gin3[35:32];end
				8:begin z<=mult_gin3[31:28];end
				9:begin z<=mult_gin3[27:24];end
				10:begin z<=mult_gin3[23:20];end
				11:begin z<=mult_gin3[19:16];end
				12:begin z<=mult_gin3[15:12];end
				13:begin z<=mult_gin3[11:8];end
				14:begin z<=mult_gin3[7:4];end
				15:begin z<=mult_gin3[3:0];end
				default: begin z<=mult_gin3[63:60];end
				endcase
			end
			else
				begin
					z<=0;
				end 
		end
 
	end
end
 
endmodule