Subversion Repositories reed_solomon_coder

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: University of Hamburg, University of Kiel, Germany
// Engineer: Cagil Gümüs, Andreas Bahr
// 
// Create Date:    14:34:38 03/24/2016 
// Design Name: 
// Module Name:    corrector 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module corrector(
	input wire clk,
	input wire reset,
	input wire go,
	input wire [3:0] location1,
	input wire [3:0] location2,
	input wire [3:0] magnitude1,
	input wire [3:0] magnitude2,
	input wire [35:0] data_in,
	output reg [35:0] data_out,
	output reg ready,
	output reg max_error
    );
 
reg [35:0] data_out_reg;
 
reg go_syndrome;
wire ready_syndrome;
wire no_errors_wire;
reg job_done_reg;
 
	syndromecalculator syndrome2(
 
	.clk(clk),
	.reset(reset),
	.data_in(data_out_reg),
	.go(go_syndrome),
	.job_done(job_done_reg),
	.syndrome_1() ,  
	.syndrome_2(),
	.syndrome_3(),
	.syndrome_4(),
	.no_errors(no_errors_wire),
	.ready(ready_syndrome)
	 );
 
 
reg [3:0]	state ;											// State Machine
 
parameter [3:0] IDLE 					= 4'b0000, 
					 LOCATION				= 4'b0001,
					 FINISH					= 4'b0011,
					 SYNDROME				= 4'b0010;
 
always@(posedge clk or negedge reset)
 
	begin
 
	if(!reset)
		begin
 
			state 				<= IDLE;
			max_error 			<= 0;
			ready 				<= 0;
			data_out 			<= 0;
			data_out_reg		<= 0;
 
		end
 
	else
		begin
			case(state)
				IDLE:
					begin
 
						go_syndrome <= 0;
						ready <= 0; 
						max_error <= 0;
						data_out_reg <= data_in;
						if(go)
							state <= LOCATION ; 
					 	else
							state <= IDLE;
					end
				LOCATION:
					begin
						job_done_reg <= 0;
						case(location1)
							//0000: data_out_reg[3:0] <= (data_out_reg[3:0]^magnitude1) 
							4'b0001: data_out_reg[3:0] 	<= (data_out_reg[3:0]	^	magnitude1);
							4'b0010: data_out_reg[7:4] 	<= (data_out_reg[7:4]	^	magnitude1);
							4'b0011: data_out_reg[19:16] 	<= (data_out_reg[19:16]	^	magnitude1);
							4'b0100: data_out_reg[11:8] 	<= (data_out_reg[11:8]	^	magnitude1);
							4'b0101: data_out_reg[35:32] 	<= (data_out_reg[35:32]	^	magnitude1);
							4'b0110: data_out_reg[23:20] 	<= (data_out_reg[23:20]	^	magnitude1);
							4'b0111: data_out_reg[7:4] 	<= (data_out_reg[7:4]	^	magnitude1);
							4'b1000: data_out_reg[15:12] 	<= (data_out_reg[15:12]	^	magnitude1);
							4'b1001: data_out_reg[23:20] 	<= (data_out_reg[23:20]	^	magnitude1);
							4'b1010: data_out_reg[3:0] 	<= (data_out_reg[3:0]	^	magnitude1);
							4'b1011: data_out_reg[31:28] 	<= (data_out_reg[31:28]	^	magnitude1);
							4'b1100: data_out_reg[27:24] 	<= (data_out_reg[27:24]	^	magnitude1);
							4'b1101: data_out_reg[19:16] 	<= (data_out_reg[19:16]	^	magnitude1);
							4'b1110: data_out_reg[11:8] 	<= (data_out_reg[11:8]	^	magnitude1);
							4'b1111: data_out_reg[15:12] 	<= (data_out_reg[15:12]	^	magnitude1);
						endcase
						case(location2)
							//0000: data_out_reg[3:0] <= (data_out_reg[3:0]^magnitude1) 
							4'b0001: data_out_reg[3:0] 	<= (data_out_reg[3:0]	^	magnitude2);
							4'b0010: data_out_reg[7:4] 	<= (data_out_reg[7:4]	^	magnitude2);
							4'b0011: data_out_reg[19:16] 	<= (data_out_reg[19:16]	^	magnitude2);
							4'b0100: data_out_reg[11:8] 	<= (data_out_reg[11:8]	^	magnitude2);
							4'b0101: data_out_reg[35:32] 	<= (data_out_reg[35:32]	^	magnitude2);
							4'b0110: data_out_reg[23:20] 	<= (data_out_reg[23:20]	^	magnitude2);
							4'b0111: data_out_reg[7:4] 	<= (data_out_reg[7:4]	^	magnitude2);
							4'b1000: data_out_reg[15:12] 	<= (data_out_reg[15:12]	^	magnitude2);
							4'b1001: data_out_reg[23:20] 	<= (data_out_reg[23:20]	^	magnitude2);
							4'b1010: data_out_reg[3:0] 	<= (data_out_reg[3:0]	^	magnitude2);
							4'b1011: data_out_reg[31:28] 	<= (data_out_reg[31:28]	^	magnitude2);
							4'b1100: data_out_reg[27:24] 	<= (data_out_reg[27:24]	^	magnitude2);
							4'b1101: data_out_reg[19:16] 	<= (data_out_reg[19:16]	^	magnitude2);
							4'b1110: data_out_reg[11:8] 	<= (data_out_reg[11:8]	^	magnitude2);
							4'b1111: data_out_reg[15:12] 	<= (data_out_reg[15:12]	^	magnitude2);
						endcase
					state <= SYNDROME;
					end
				SYNDROME:
					begin
						go_syndrome <= 1;
						if(ready_syndrome)
							begin
								state <= FINISH;
							end
						else
							begin
								state	<= SYNDROME;
							end
					end
				FINISH: 
					begin
						if(no_errors_wire)
							max_error <= 0;
						else
							max_error <= 1;
						data_out <= data_out_reg;
						job_done_reg <= 1;
						state <= IDLE; 
						ready <= 1;
					end
				default:	state <= IDLE ;
			endcase
		end 
end
 
endmodule