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<title>Encryption Block</title>
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<div class=Section1>
<h1>Encryption Block</h1>
<h2><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;font-family:Arial'>John
Purba (</span><a href="mailto:john@students.ee.itb.ac.id">john@students.ee.itb.ac.id</a><span
style='font-size:10.0pt;mso-bidi-font-size:12.0pt;font-family:Arial'>)<o:p></o:p></span></h2>
<p class=MsoNormal><![if !supportEmptyParas]> <![endif]><o:p></o:p></p>
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'>The encryption block comprises 6 blocks:<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>
</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'>Data & Key Input Register, interface of input data and
key<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>
</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'>Key Expander, generator the round key<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>
</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'>Control, controls each block <o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>
</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'>Rijndael Alg, implements Rijndael algorithm (round
calculations)<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>
</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'>Data Output Register, interface of output data<o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'><![if !supportEmptyParas]> <![endif]><o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'>The RTL VHDL code can be downloaded here <a
href="enkrip_files\enkrip.zip"><span style='font-size:12.0pt;font-family:"Times New Roman"'>enkrip.zip</span></a><o:p></o:p></span></p>
<p class=MsoNormal style='mso-layout-grid-align:none;text-autospace:none'><span
style='font-size:10.0pt;mso-bidi-font-size:12.0pt;font-family:Arial'>The
encryption algorithm has been designed this way that the generation of round
key and the round calculations can be parallely executed. </span><span
style='font-size:10.0pt;font-family:Arial'>The advantage of this design is the
fact that we do not need to store the round key since they are currently
calculated. Interconnection of each block is depicted in figure 1.<o:p></o:p></span></p>
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<p class=MsoNormal align=center style='text-align:center'><span
style='font-family:Arial'>Figure 1<o:p></o:p></span></p>
<p class=MsoNormal align=center style='text-align:center'><a
name="Data_Kunci_Reg"><![if !supportEmptyParas]> <![endif]><o:p></o:p></a></p>
<p class=MsoNormal><span style='mso-bookmark:Data_Kunci_Reg'><span
style='font-size:16.0pt;mso-bidi-font-size:12.0pt;font-family:Arial'>1. Data
& Key Input Register</span></span><span style='font-size:16.0pt;mso-bidi-font-size:
12.0pt;font-family:Arial'><o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'><span style='mso-tab-count:1'> </span>This block is
data or key input interface. The length of data or key supported is 128 bits,
so we can use the same design for data input and key input. This block will
take 32 bits data and shifts them to next register. Four clock cycle will be
needed to take a complete 128 bit data. A simple controller is used here to
identify that a complete of 128 bits data has been accepted. The State Diagram
of FSMInput and Data or Key Input Register is depicted in figure 2.<o:p></o:p></span></p>
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</v:shape><![endif]--><![if !vml]><img border=0 width=660 height=449
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<p class=MsoNormal align=center style='text-align:center'><span
style='font-family:Arial'>Figure 2</span><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'><o:p></o:p></span></p>
<p class=MsoNormal><a name="Data_Reg"><span style='font-size:16.0pt;mso-bidi-font-size:
12.0pt;font-family:Arial'>2. Data Output Register</span></a><span
style='font-size:16.0pt;mso-bidi-font-size:12.0pt;font-family:Arial'><o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'><span style='mso-tab-count:1'> </span>This block
takes 128 bit block data to output. First one block of 128 bits is divided to 4
blocks of 32 bits. One block of 32 bits data is take to output every one clock cycle.
Data output register is depicted in figure 3.<o:p></o:p></span></p>
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<v:imagedata src="./enkrip_files/image010.wmz" o:title=""/>
</v:shape><![endif]--><![if !vml]><img border=0 width=618 height=252
src="./enkrip_files/image011.gif" v:shapes="_x0000_i1065"><![endif]><!--[if gte mso 9]><xml>
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<p class=MsoNormal align=center style='text-align:center'><span
style='font-family:Arial'>Figure 3</span><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'><o:p></o:p></span></p>
<p class=MsoNormal><a name=Control><span style='font-size:16.0pt;mso-bidi-font-size:
12.0pt;font-family:Arial'>3. Control</span></a><span style='font-size:16.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'><o:p></o:p></span></p>
<p class=MsoBodyText><span style='mso-tab-count:1'> </span>The
Control block controls the Key Expander and Rijndael Alg block. The state
diagram of Control block is depicted in figure 4.</p>
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<v:imagedata src="./enkrip_files/image012.wmz" o:title=""/>
</v:shape><![endif]--><![if !vml]><img border=0 width=256 height=432
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<o:OLEObject Type="Embed" ProgID="Visio.Drawing.5" ShapeID="_x0000_i1136"
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</xml><![endif]--><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'><o:p></o:p></span></p>
<p class=MsoNormal align=center style='text-align:center'><span
style='font-family:Arial'>Figure 4<o:p></o:p></span></p>
<p class=MsoNormal><a name="Key_Expander"><span style='font-size:16.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'>4. Key Expander<o:p></o:p></span></a></p>
<p class=MsoBodyText><span style='mso-bookmark:Key_Expander'><span
style='mso-tab-count:1'> </span>Key Expander responsible to generate
round key for every round from the initial key. Based on the algorithm
specification, if we use 128-bit key, 10 rounds will be needed. Hence the Key
Expander will generate 10 round keys. The Key Expander is depicted in figure 5.
</span></p>
<span style='mso-bookmark:Key_Expander'></span>
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font-family:Arial'><![if !supportEmptyParas]> <![endif]><o:p></o:p></span></p>
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<p class=MsoNormal align=center style='text-align:center'><span
style='font-family:Arial'>Figure 5<o:p></o:p></span></p>
<p class=MsoNormal align=center style='text-align:center'><span
style='font-family:Arial'><![if !supportEmptyParas]> <![endif]><o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'>The Blok Alg implements the XOR operations and RotByte function.
Kontroler Internal controls the Key Expander and its state diagram illustrated
in figure 6. The ByteSub block is the same as ByteSub for Rijndael Alg Block.<o:p></o:p></span></p>
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font-family:Arial'><![if !supportEmptyParas]> <![endif]><o:p></o:p></span></p>
<h3>State Diagram of Kontroler Internal</h3>
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<p class=MsoNormal align=center style='text-align:center'><![if !supportEmptyParas]> <![endif]><o:p></o:p></p>
<p class=MsoNormal align=center style='text-align:center'><span
style='font-family:Arial'>Figure 6</span><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'><o:p></o:p></span></p>
<p class=MsoNormal><a name="Rijndael_alg"><span style='font-size:16.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'>5. Rijndael Alg</span></a><span
style='font-size:16.0pt;mso-bidi-font-size:12.0pt;font-family:Arial'><o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'><span style='mso-tab-count:1'> </span>The
implementation of Rijndael Alg has been designed this way that it can work as
the initial round, standard round, and final round. The Rijndael Alg module is
depicted in figure 7. <o:p></o:p></span></p>
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<p class=MsoNormal align=center style='text-align:center'><span
style='font-family:Arial'>Figure 7<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;mso-bidi-font-weight:bold'>-<span style='font:7.0pt "Times New Roman"'>
</span></span><![endif]><b><span style='font-size:10.0pt;mso-bidi-font-size:
12.0pt;font-family:Arial'>Mux21<o:p></o:p></span></b></p>
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'>Mux21 is a simple multiplexer 2 to
1. The format of data (din_i) is changed in this block, a block 128 bits sequence
to matrix 4x4 called State, as it is easier to design another blocks
(AddRoundKey, ByteSub, ShiftRow. MixColumn) <o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'><![if !supportEmptyParas]> <![endif]><o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;mso-bidi-font-weight:bold'>-<span style='font:7.0pt "Times New Roman"'>
</span></span><![endif]><b><span style='font-size:10.0pt;mso-bidi-font-size:
12.0pt;font-family:Arial'>AddRoundKey<o:p></o:p></span></b></p>
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'>Implements AddRoundKey transformation,
a simple XOR between State and round key. <o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'><![if !supportEmptyParas]> <![endif]><o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;mso-bidi-font-weight:bold'>-<span style='font:7.0pt "Times New Roman"'>
</span></span><![endif]><b><span style='font-size:10.0pt;mso-bidi-font-size:
12.0pt;font-family:Arial'>ByteSub<o:p></o:p></span></b></p>
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'>Implements ByteSub transformation,
contains 16 S-Box working in parallel. Dual Port Block RAM will be used to implements
2 S-Box, which emulate the ROM memory with configuration of 256x8 bits.<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'><![if !supportEmptyParas]> <![endif]><o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;mso-bidi-font-weight:bold'>-<span style='font:7.0pt "Times New Roman"'>
</span></span><![endif]><b><span style='font-size:10.0pt;mso-bidi-font-size:
12.0pt;font-family:Arial'>ShiftRow<o:p></o:p></span></b></p>
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'>Implements ShiftRow transformation.
The position of bytes in State will shifted cyclical by offsets. The first row
is shifted by zero, the second row is shifter by one, the third row is shifted
by two, and the fourth row is shifted by three. The implementation is realized
by hardwiring and do not need gate resource.<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'><![if !supportEmptyParas]> <![endif]><o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;mso-bidi-font-weight:bold'>-<span style='font:7.0pt "Times New Roman"'>
</span></span><![endif]><b><span style='font-size:10.0pt;mso-bidi-font-size:
12.0pt;font-family:Arial'>MixColumn<o:p></o:p></span></b></p>
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'>Implements MixColumn transformation.
The columns of State are viewed as the coefficients of polynomial over GF (2<sup>8</sup>)
of degree smaller than three. This polynomial is multiplied by four terms fixed
polynomial a(x), {03)x<sup>3</sup> + {01}x<sup>2</sup> + {01}x + {02}, modulo
the polynomial x<sup>4</sup> + 1.The multiplication with four terms fixed
polynomial can be simplified by using the matrix form. The implementation of
this transformation can be realized as shift and XOR operations.<o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'><![if !supportEmptyParas]> <![endif]><o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'><![if !supportEmptyParas]> <![endif]><o:p></o:p></span></p>
<h4><b>Implementation Result<o:p></o:p></b></h4>
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'><span style='mso-tab-count:1'> </span>The
encryption algorithm has been implemented to FPGA Xilinx Virtex V300PQ240. It
has 20 Dual Port Block RAM to implement to ByteSub transformation. The
implementation parameters are:<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>
</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'>Speed<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'>The maximum frequency is 51 MHz
corresponds to throughput 298,899 Mbps.<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>
</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
font-family:Arial'>Area<o:p></o:p></span></p>
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
mso-bidi-font-size:12.0pt;font-family:Arial'>The design required 666 slices<o:p></o:p></span></p>
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