OpenCores
URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [examples/] [dhrystone21/] [src/] [main.cpp] - Rev 5

Compare with Previous | Blame | View Log

//****************************************************************************
//
//****************************************************************************
#include "uart.h"
 
extern "C" int shell_cmd_soc_dhry(int argc, char *argv[]);
 
void *__gxx_personality_v0;
 
//****************************************************************************
int __attribute__((__section__(".text.entrypoint"))) main()
{
  int argc = 0;
  char *argv[1] = {0};
 
  uart_init();
 
  shell_cmd_soc_dhry(argc, argv);
 
  printf_uart("%s[%d]: End of test\n", __FUNCTION__, __LINE__);
 
  return 0;
}
 
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.